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Searched refs:MemVT (Results 1 – 25 of 40) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1106 SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
1112 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain,
1117 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT,
1122 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
1132 EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
1139 EVT MemVT, MachinePointerInfo PtrInfo, MaybeAlign Alignment = None,
1144 return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
1145 Alignment.getValueOr(getEVTAlign(MemVT)), Flags,
1150 ArrayRef<SDValue> Ops, EVT MemVT,
1193 SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT,
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H A DTargetLowering.h574 virtual bool storeOfVectorConstantIsCheap(EVT MemVT, in storeOfVectorConstantIsCheap() argument
583 virtual bool mergeStoresAfterLegalization(EVT MemVT) const { in mergeStoresAfterLegalization() argument
588 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, in canMergeStoresTo() argument
1221 EVT MemVT) const { in getLoadExtAction() argument
1222 if (ValVT.isExtended() || MemVT.isExtended()) return Expand; in getLoadExtAction()
1224 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction()
1232 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
1233 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
1238 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
1239 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
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H A DSelectionDAGNodes.h1397 EVT MemVT, MachineMemOperand *MMO)
1398 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
2221 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2223 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2255 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2257 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2283 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2285 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2316 ISD::MemIndexedMode AM, EVT MemVT,
2318 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
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H A DBasicTTIImpl.h1100 EVT MemVT = getTLI()->getValueType(DL, Src); variable
1102 LA = getTLI()->getTruncStoreAction(LT.second, MemVT);
1104 LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1074 EVT MemVT = Store->getMemoryVT(); in lowerPrivateTruncStore() local
1107 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1148 EVT MemVT = StoreNode->getMemoryVT(); in LowerSTORE() local
1165 MemVT, StoreNode->getAlignment(), in LowerSTORE()
1174 if (Alignment < MemVT.getStoreSize() && in LowerSTORE()
1175 !allowsMisalignedMemoryAccesses(MemVT, AS, Alignment, in LowerSTORE()
1190 if (MemVT == MVT::i8) { in LowerSTORE()
1193 assert(MemVT == MVT::i16); in LowerSTORE()
1221 Op->getVTList(), Args, MemVT, in LowerSTORE()
1240 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
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H A DSIISelLowering.h50 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
116 ArrayRef<SDValue> Ops, EVT MemVT,
130 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
160 EVT MemVT,
271 bool canMergeStoresTo(unsigned AS, EVT MemVT,
H A DAMDGPUISelLowering.cpp854 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT, in storeOfVectorConstantIsCheap() argument
1053 EVT MemVT = ArgVT; in analyzeFormalArgumentsCompute() local
1062 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1064 MemVT = ArgVT; in analyzeFormalArgumentsCompute()
1072 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1077 MemVT = ArgVT.getScalarType(); in analyzeFormalArgumentsCompute()
1080 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1085 MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits); in analyzeFormalArgumentsCompute()
1094 MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements); in analyzeFormalArgumentsCompute()
1101 if (MemVT.isVector() && MemVT.getVectorNumElements() == 1) in analyzeFormalArgumentsCompute()
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H A DSIISelLowering.cpp1385 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT, in canMergeStoresTo() argument
1388 return (MemVT.getSizeInBits() <= 4 * 32); in canMergeStoresTo()
1391 return (MemVT.getSizeInBits() <= MaxPrivateBits); in canMergeStoresTo()
1393 return (MemVT.getSizeInBits() <= 2 * 32); in canMergeStoresTo()
1639 SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT, in convertArgType() argument
1645 VT.getVectorNumElements() != MemVT.getVectorNumElements()) { in convertArgType()
1647 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(), in convertArgType()
1655 VT.bitsLT(MemVT)) { in convertArgType()
1657 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT)); in convertArgType()
1660 if (MemVT.isFloatingPoint()) in convertArgType()
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H A DR600ISelLowering.h49 bool canMergeStoresTo(unsigned AS, EVT MemVT,
H A DAMDGPUISelLowering.h185 bool storeOfVectorConstantIsCheap(EVT MemVT,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp681 EVT &MemVT, unsigned ShAmt = 0);
701 EVT MemVT, unsigned NumStores,
730 EVT MemVT, SDNode *Root, bool AllowVectors);
737 unsigned NumConsecutiveStores, EVT MemVT,
743 unsigned NumConsecutiveStores, EVT MemVT,
1212 EVT MemVT = LD->getMemoryVT(); in PromoteOperand() local
1218 MemVT, LD->getMemOperand()); in PromoteOperand()
1449 EVT MemVT = LD->getMemoryVT(); in PromoteLoad() local
1454 MemVT, LD->getMemOperand()); in PromoteLoad()
5229 ISD::LoadExtType ExtType, EVT &MemVT, in isLegalNarrowLdSt() argument
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H A DSelectionDAG.cpp7034 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, in getAtomic() argument
7038 ID.AddInteger(MemVT.getRawBits()); in getAtomic()
7048 VTList, MemVT, MMO); in getAtomic()
7057 EVT MemVT, SDVTList VTs, SDValue Chain, in getAtomicCmpSwap() argument
7065 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO); in getAtomicCmpSwap()
7068 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, in getAtomic() argument
7093 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO); in getAtomic()
7096 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, in getAtomic() argument
7103 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO); in getAtomic()
7120 EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, in getMemIntrinsicNode() argument
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H A DSelectionDAGBuilder.cpp2453 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType()); in visitSwitchCase() local
2472 if (CondLHS.getValueType() != MemVT) { in visitSwitchCase()
2473 CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT); in visitSwitchCase()
2474 CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT); in visitSwitchCase()
3196 EVT MemVT = in visitICmp() local
3202 if (Op1.getValueType() != MemVT) { in visitICmp()
3203 Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT); in visitICmp()
3204 Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT); in visitICmp()
4579 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType(); in visitAtomicCmpXchg() local
4580 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other); in visitAtomicCmpXchg()
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H A DLegalizeDAG.cpp510 EVT MemVT = ST->getMemoryVT(); in LegalizeStoreOps() local
512 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT, in LegalizeStoreOps()
620 EVT MemVT = ST->getMemoryVT(); in LegalizeStoreOps() local
623 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT, in LegalizeStoreOps()
681 EVT MemVT = LD->getMemoryVT(); in LegalizeLoadOps() local
685 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT, in LegalizeLoadOps()
866 EVT MemVT = LD->getMemoryVT(); in LegalizeLoadOps() local
868 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, in LegalizeLoadOps()
1436 EVT MemVT = isa<BuildVectorSDNode>(Node) ? VT.getVectorElementType() in ExpandVectorBuildThroughStack() local
1446 unsigned TypeByteSize = MemVT.getSizeInBits() / 8; in ExpandVectorBuildThroughStack()
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H A DLegalizeVectorTypes.cpp1090 void DAGTypeLegalizer::IncrementPointer(MemSDNode *N, EVT MemVT, in IncrementPointer() argument
1094 unsigned IncrementSize = MemVT.getSizeInBits().getKnownMinSize() / 8; in IncrementPointer()
1096 if (MemVT.isScalableVector()) { in IncrementPointer()
5161 EVT MemVT((MVT::SimpleValueType) VT); in FindMemType() local
5162 unsigned MemVTWidth = MemVT.getSizeInBits(); in FindMemType()
5163 if (MemVT.getSizeInBits() <= WidenEltWidth) in FindMemType()
5165 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT); in FindMemType()
5173 return MemVT; in FindMemType()
5174 RetVT = MemVT; in FindMemType()
5184 EVT MemVT = (MVT::SimpleValueType) VT; in FindMemType() local
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.h987 bool mergeStoresAfterLegalization(EVT MemVT) const override { in mergeStoresAfterLegalization() argument
988 return !MemVT.isVector(); in mergeStoresAfterLegalization()
991 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
1322 bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, in storeOfVectorConstantIsCheap() argument
H A DX86ISelDAGToDAG.cpp1238 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG() local
1239 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); in PreprocessISelDAG()
1248 CurDAG->getEntryNode(), dl, N->getOperand(0), MemTmp, MPI, MemVT); in PreprocessISelDAG()
1250 MemTmp, MPI, MemVT); in PreprocessISelDAG()
1294 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG() local
1295 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); in PreprocessISelDAG()
1308 Store = CurDAG->getMemIntrinsicNode(X86ISD::FST, dl, VTs, Ops, MemVT, in PreprocessISelDAG()
1317 assert(SrcVT == MemVT && "Unexpected VT!"); in PreprocessISelDAG()
1326 X86ISD::FLD, dl, VTs, Ops, MemVT, MPI, in PreprocessISelDAG()
1334 assert(DstVT == MemVT && "Unexpected VT!"); in PreprocessISelDAG()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1345 EVT MemVT = StoreNode->getMemoryVT(); in tryFoldLoadStoreIntoMemOperand() local
1355 if (MemVT == MVT::i32) in tryFoldLoadStoreIntoMemOperand()
1357 else if (MemVT == MVT::i64) in tryFoldLoadStoreIntoMemOperand()
1366 if (MemVT == MVT::i32) in tryFoldLoadStoreIntoMemOperand()
1368 else if (MemVT == MVT::i64) in tryFoldLoadStoreIntoMemOperand()
1390 Operand = CurDAG->getTargetConstant(OperandV, DL, MemVT); in tryFoldLoadStoreIntoMemOperand()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp752 MVT MemVT; in getTgtMemIntrinsic() local
756 MemVT = MVT::i8; in getTgtMemIntrinsic()
760 MemVT = MVT::i16; in getTgtMemIntrinsic()
764 MemVT = MVT::i32; in getTgtMemIntrinsic()
768 MemVT = MVT::i64; in getTgtMemIntrinsic()
784 Info.memVT = MemVT; in getTgtMemIntrinsic()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.h667 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, in canMergeStoresTo() argument
670 return (MemVT.getSizeInBits() <= 32); in canMergeStoresTo()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2650 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); in createLoadLR() local
2660 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createLoadLR()
2667 EVT MemVT = LD->getMemoryVT(); in lowerLOAD() local
2673 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || in lowerLOAD()
2674 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) in lowerLOAD()
2732 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); in createStoreLR() local
2741 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createStoreLR()
2793 EVT MemVT = SD->getMemoryVT(); in lowerSTORE() local
2797 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && in lowerSTORE()
2798 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) in lowerSTORE()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4181 void selectGatherScatterAddrMode(SDValue &BasePtr, SDValue &Index, EVT MemVT, in selectGatherScatterAddrMode() argument
4209 unsigned ScalarSizeInBytes = MemVT.getScalarSizeInBits() / 8; in selectGatherScatterAddrMode()
4249 EVT MemVT = MGT->getMemoryVT(); in LowerMGATHER() local
4250 SDValue InputVT = DAG.getValueType(MemVT); in LowerMGATHER()
4260 InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger()); in LowerMGATHER()
4269 selectGatherScatterAddrMode(BasePtr, Index, MemVT, Opcode, in LowerMGATHER()
4309 EVT MemVT = MSC->getMemoryVT(); in LowerMSCATTER() local
4310 SDValue InputVT = DAG.getValueType(MemVT); in LowerMSCATTER()
4320 InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger()); in LowerMSCATTER()
4327 selectGatherScatterAddrMode(BasePtr, Index, MemVT, Opcode, in LowerMSCATTER()
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H A DAArch64SVEInstrInfo.td2029 SDPatternOperator Load, ValueType PredTy, ValueType MemVT, ComplexPattern AddrCP> {
2032 def : Pat<(Ty (Load (PredTy PPR:$gp), (AddrCP GPR64:$base, GPR64:$offset), MemVT)),
2038 …def : Pat<(Ty (Load (PredTy PPR:$gp), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), MemVT)),
2043 def : Pat<(Ty (Load (PredTy PPR:$gp), GPR64:$base, MemVT)),
2075 …ass ldnf1<Instruction I, ValueType Ty, SDPatternOperator Load, ValueType PredTy, ValueType MemVT> {
2078 …def : Pat<(Ty (Load (PredTy PPR:$gp), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), MemVT)),
2083 def : Pat<(Ty (Load (PredTy PPR:$gp), GPR64:$base, MemVT)),
2115 …tion I, ValueType Ty, SDPatternOperator Load, ValueType PredTy, ValueType MemVT, ComplexPattern Ad…
2118 def : Pat<(Ty (Load (PredTy PPR:$gp), (AddrCP GPR64:$base, GPR64:$offset), MemVT)),
2123 def : Pat<(Ty (Load (PredTy PPR:$gp), GPR64:$base, MemVT)),
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H A DAArch64ISelLowering.h702 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, in canMergeStoresTo() argument
711 return (MemVT.getSizeInBits() <= 64); in canMergeStoresTo()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp2885 EVT MemVT = LD->getMemoryVT(); in usePartialVectorLoads() local
2886 if (!MemVT.isSimple()) in usePartialVectorLoads()
2888 switch(MemVT.getSimpleVT().SimpleTy) { in usePartialVectorLoads()
8156 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT, in canReuseLoadAddress() argument
8180 if (LD->getMemoryVT() != MemVT) in canReuseLoadAddress()
10441 EVT MemVT = AtomicNode->getMemoryVT(); in LowerATOMIC_CMP_SWAP() local
10442 if (MemVT.getSizeInBits() >= 32) in LowerATOMIC_CMP_SWAP()
10447 auto HighBits = APInt::getHighBitsSet(32, 32 - MemVT.getSizeInBits()); in LowerATOMIC_CMP_SWAP()
10452 unsigned MaskVal = (1 << MemVT.getSizeInBits()) - 1; in LowerATOMIC_CMP_SWAP()
10465 (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 : PPCISD::ATOMIC_CMP_SWAP_16; in LowerATOMIC_CMP_SWAP()
[all …]

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