| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 259 Register MaskReg, Register ScratchReg) { in insertMaskedMerge() argument
261 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in insertMaskedMerge()
262 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
272 .addReg(MaskReg); in insertMaskedMerge()
287 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
329 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, in doMaskedAtomicBinOpExpansion()
427 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
443 .addReg(MaskReg); in expandAtomicMinMaxOp()
486 MaskReg, Scratch1Reg); in expandAtomicMinMaxOp()
568 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 213 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy); in buildMaskLowPtrBits() local
214 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits()
215 return buildPtrMask(Res, Op0, MaskReg); in buildMaskLowPtrBits()
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| H A D | LegalizerHelper.cpp | 6806 Register MaskReg = MI.getOperand(1).getReg(); in lowerSelect() local
6810 LLT MaskTy = MRI.getType(MaskReg); in lowerSelect()
6818 Register MaskElt = MaskReg; in lowerSelect()
6833 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); in lowerSelect()
6834 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); in lowerSelect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 355 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
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| H A D | AArch64InstrInfo.cpp | 1306 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr() argument
1308 auto *Mask = MRI->getUniqueVRegDef(MaskReg); in optimizePTestInstr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2488 Register MaskReg = I.getOperand(2).getReg(); in selectG_PTRMASK() local
2490 LLT MaskTy = MRI->getType(MaskReg); in selectG_PTRMASK()
2494 const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI); in selectG_PTRMASK()
2512 !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI)) in selectG_PTRMASK()
2523 .addReg(MaskReg); in selectG_PTRMASK()
2541 APInt MaskOnes = KnownBits->getKnownOnes(MaskReg).zextOrSelf(64); in selectG_PTRMASK()
2554 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
2568 .addReg(MaskReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11221 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
11297 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
11311 .addReg(MaskReg); in EmitPartwordAtomicBinary()
11312 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
11319 .addReg(MaskReg); in EmitPartwordAtomicBinary()
12230 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
12316 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
12321 .addReg(MaskReg); in EmitInstrWithCustomInserter()
12324 .addReg(MaskReg); in EmitInstrWithCustomInserter()
12332 .addReg(MaskReg); in EmitInstrWithCustomInserter()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2798 Register MaskReg = I.getOperand(2).getReg(); in select() local
2799 Optional<int64_t> MaskVal = getConstantVRegSExtVal(MaskReg, MRI); in select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4763 Register MaskReg = MIB.getReg(1); in expandPostRAPseudo() local
4771 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState) in expandPostRAPseudo()
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