Home
last modified time | relevance | path

Searched refs:MaskLo (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1745 SDValue MaskLo, MaskHi; in SplitVecRes_MLOAD() local
1747 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi); in SplitVecRes_MLOAD()
1750 GetSplitVector(Mask, MaskLo, MaskHi); in SplitVecRes_MLOAD()
1752 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl); in SplitVecRes_MLOAD()
1772 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, Offset, MaskLo, PassThruLo, LoMemVT, in SplitVecRes_MLOAD()
1782 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG, in SplitVecRes_MLOAD()
1830 SDValue MaskLo, MaskHi; in SplitVecRes_MGATHER() local
1832 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi); in SplitVecRes_MGATHER()
1835 GetSplitVector(Mask, MaskLo, MaskHi); in SplitVecRes_MGATHER()
1837 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl); in SplitVecRes_MGATHER()
[all …]
H A DTargetLowering.cpp1861 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth); in SimplifyDemandedBits() local
1866 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1)) in SimplifyDemandedBits()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2550 Register MaskLo = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
2553 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskLo) in selectG_PTRMASK()
2557 .addReg(MaskLo); in selectG_PTRMASK()
H A DAMDGPURegisterBankInfo.cpp2557 Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0); in applyMappingImpl() local
2558 MRI.setRegBank(MaskLo, *BankLo); in applyMappingImpl()
2566 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0); in applyMappingImpl()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp23261 static const int MaskLo[] = { 0, 0, 2, 2 }; in LowerVSETCC() local
23263 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo); in LowerVSETCC()