| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 32 class MachineInstr; variable
43 MachineInstr *MI;
64 MachineInstr *Logic;
65 MachineInstr *Shift2;
124 bool tryCombineCopy(MachineInstr &MI);
125 bool matchCombineCopy(MachineInstr &MI);
126 void applyCombineCopy(MachineInstr &MI);
130 bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
138 bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
142 bool tryCombineExtendingLoads(MachineInstr &MI);
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| H A D | LegalizerHelper.h | 81 LegalizeResult legalizeInstrStep(MachineInstr &MI);
84 LegalizeResult libcall(MachineInstr &MI);
88 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
93 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
96 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
100 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
104 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
109 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
123 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
129 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 34 class MachineInstr; variable
57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
208 const MachineInstr &LdSt,
223 bool isPredicated(const MachineInstr &MI) const override;
226 bool isPostIncrement(const MachineInstr &MI) const override;
230 bool PredicateInstruction(MachineInstr &MI,
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| H A D | HexagonVLIWPacketizer.h | 23 class MachineInstr; variable
29 std::vector<MachineInstr *> OldPacketMIs;
54 std::vector<MachineInstr*> IgnoreDepMIs;
86 bool ignorePseudoInstruction(const MachineInstr &MI,
91 bool isSoloInstruction(const MachineInstr &MI) override;
102 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
105 bool shouldAddToPacket(const MachineInstr &MI) override;
116 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
118 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
121 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.h | 42 class MachineInstr; variable
62 bool select(MachineInstr &I) override;
71 const MachineInstr &GEP;
75 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } in GEPInfo()
80 bool isInstrUniform(const MachineInstr &MI) const;
88 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
94 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
95 bool selectCOPY(MachineInstr &I) const;
96 bool selectPHI(MachineInstr &I) const;
97 bool selectG_TRUNC(MachineInstr &I) const;
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| H A D | GCNHazardRecognizer.h | 25 class MachineInstr; variable
35 typedef function_ref<bool(const MachineInstr &)> IsHazardFn;
44 MachineInstr *CurrCycleInstr;
45 std::list<MachineInstr*> EmittedInstrs;
63 void addClauseInst(const MachineInstr &MI);
73 int checkSoftClauseHazards(MachineInstr *SMEM);
74 int checkSMRDHazards(MachineInstr *SMRD);
75 int checkVMEMHazards(MachineInstr* VMEM);
76 int checkDPPHazards(MachineInstr *DPP);
77 int checkDivFMasHazards(MachineInstr *DivFMas);
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| H A D | AMDGPULegalizerInfo.h | 39 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
45 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
60 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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| H A D | SIInstrInfo.h | 56 using SetVectorType = SmallSetVector<MachineInstr *, 32>;
75 void swapOperands(MachineInstr &Inst) const;
78 moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
81 void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
85 MachineInstr &Inst) const;
88 MachineInstr &Inst) const;
91 MachineInstr &Inst,
95 MachineInstr &Inst,
99 MachineInstr &Inst, unsigned Opcode,
102 void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
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| H A D | R600InstrInfo.h | 35 class MachineInstr; variable
45 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
92 bool canBeConsideredALU(const MachineInstr &MI) const;
95 bool isTransOnly(const MachineInstr &MI) const;
97 bool isVectorOnly(const MachineInstr &MI) const;
101 bool usesVertexCache(const MachineInstr &MI) const;
103 bool usesTextureCache(const MachineInstr &MI) const;
106 bool usesAddressRegister(MachineInstr &MI) const;
107 bool definesAddressRegister(MachineInstr &MI) const;
108 bool readsLDSSrcReg(const MachineInstr &MI) const;
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| H A D | AMDGPURegisterBankInfo.h | 52 MachineInstr &MI,
63 MachineInstr &MI,
66 bool executeInWaterfallLoop(MachineInstr &MI,
70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
72 bool applyMappingDynStackAlloc(MachineInstr &MI,
75 bool applyMappingLoad(MachineInstr &MI,
79 applyMappingImage(MachineInstr &MI,
93 MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
94 MachineInstr &MI) const;
103 getInstrMappingForLoad(const MachineInstr &MI) const;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 124 bool isTriviallyReMaterializable(const MachineInstr &MI,
140 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
160 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
183 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
196 bool isFrameInstr(const MachineInstr &I) const { in isFrameInstr()
202 bool isFrameSetup(const MachineInstr &I) const { in isFrameSetup()
214 int64_t getFrameSize(const MachineInstr &I) const { in getFrameSize()
223 int64_t getFrameTotalSize(const MachineInstr &I) const { in getFrameTotalSize()
239 virtual int getSPAdjust(const MachineInstr &MI) const;
246 virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, in isCoalescableExtInstr()
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| H A D | ReachingDefAnalysis.h | 34 class MachineInstr; variable
94 DenseMap<MachineInstr *, int> InstIds;
107 using InstSet = SmallPtrSetImpl<MachineInstr*>;
142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
145 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B,
150 bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const;
154 MachineInstr *getLocalLiveOutMIDef(MachineBasicBlock *MBB,
159 MachineInstr *getUniqueReachingMIDef(MachineInstr *MI,
164 MachineInstr *getMIOperand(MachineInstr *MI, unsigned Idx) const;
168 MachineInstr *getMIOperand(MachineInstr *MI, MachineOperand &MO) const;
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| H A D | ModuloSchedule.h | 73 class MachineInstr; variable
86 std::vector<MachineInstr *> ScheduledInstrs;
89 DenseMap<MachineInstr *, int> Cycle;
92 DenseMap<MachineInstr *, int> Stage;
106 std::vector<MachineInstr *> ScheduledInstrs, in ModuloSchedule()
107 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
108 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule()
133 int getStage(MachineInstr *MI) { in getStage()
139 int getCycle(MachineInstr *MI) { in getCycle()
145 void setStage(MachineInstr *MI, int MIStage) { in setStage()
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| H A D | LiveVariables.h | 89 std::vector<MachineInstr*> Kills;
94 bool removeKill(MachineInstr &MI) { in removeKill()
95 std::vector<MachineInstr *>::iterator I = find(Kills, &MI); in removeKill()
103 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
135 std::vector<MachineInstr *> PhysRegDef;
140 std::vector<MachineInstr *> PhysRegUse;
146 DenseMap<MachineInstr*, unsigned> DistanceMap;
151 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
156 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
157 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 33 AC_EVEX_2_VEX = MachineInstr::TAsmComments
47 CondCode getCondFromBranch(const MachineInstr &MI);
50 CondCode getCondFromSETCC(const MachineInstr &MI);
53 CondCode getCondFromCMov(const MachineInstr &MI);
110 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { in isLeaMem()
123 inline static bool isMem(const MachineInstr &MI, unsigned Op) { in isMem()
139 SmallVectorImpl<MachineInstr *> &CondBranches,
153 int64_t getFrameAdjustment(const MachineInstr &I) const { in getFrameAdjustment()
162 void setFrameAdjustment(MachineInstr &I, int64_t V) const { in setFrameAdjustment()
173 int getSPAdjust(const MachineInstr &MI) const override;
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| H A D | X86FastTileConfig.cpp | 48 MachineInstr *getTileConfigPoint();
55 bool isTileLoad(MachineInstr &MI);
56 bool isTileStore(MachineInstr &MI);
57 bool isAMXInstr(MachineInstr &MI);
58 void getTileStoreShape(MachineInstr &MI,
61 MachineInstr *getKeyAMXInstr(MachineInstr *MI);
62 void getTileShapesCfg(MachineInstr *MI,
64 void getShapeCfgInstrs(MachineInstr *MI,
65 std::map<unsigned, MachineInstr *> &RowCfgs,
66 std::map<unsigned, MachineInstr *> &ColCfgs);
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| H A D | X86AsmPrinter.h | 82 void LowerSTACKMAP(const MachineInstr &MI);
83 void LowerPATCHPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
84 void LowerSTATEPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
85 void LowerFAULTING_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
86 void LowerPATCHABLE_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
88 void LowerTlsAddr(X86MCInstLower &MCInstLowering, const MachineInstr &MI);
91 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
93 void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL);
94 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
95 void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 196 SmallVectorImpl<MachineInstr *> &NewMIs) const;
200 SmallVectorImpl<MachineInstr *> &NewMIs) const;
204 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
205 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
208 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
212 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
214 MachineInstr &DefMI) const;
217 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
218 unsigned ConstantOpNo, MachineInstr &DefMI,
225 MachineInstr *getForwardingDefMI(MachineInstr &MI,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.h | 39 getInstrMapping(const MachineInstr &MI) const override;
50 void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const;
125 SmallVector<MachineInstr *, 2> DefUses;
126 SmallVector<MachineInstr *, 2> UseDefs;
136 MachineInstr *skipCopiesOutgoing(MachineInstr *MI) const;
143 MachineInstr *skipCopiesIncoming(MachineInstr *MI) const;
146 AmbiguousRegDefUseContainer(const MachineInstr *MI);
147 SmallVectorImpl<MachineInstr *> &getDefUses() { return DefUses; } in getDefUses()
148 SmallVectorImpl<MachineInstr *> &getUseDefs() { return UseDefs; } in getUseDefs()
156 DenseMap<const MachineInstr *, SmallVector<const MachineInstr *, 2>>
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 50 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
52 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
54 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
58 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
59 const MachineInstr &MIb) const override;
61 unsigned isLoadFromStackSlot(const MachineInstr &MI,
63 unsigned isStoreToStackSlot(const MachineInstr &MI,
67 static bool isGPRZero(const MachineInstr &MI);
70 static bool isGPRCopy(const MachineInstr &MI);
73 static bool isFPRCopy(const MachineInstr &MI);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 66 MachineInstr *tryToCombine(MachineInstr &Ldst);
69 bool noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
70 const MachineInstr *Ldst);
74 bool canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
78 bool canSinkLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
84 MachineInstr *canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
85 SmallVectorImpl<MachineInstr *> *Uses);
89 bool canFixPastUses(const ArrayRef<MachineInstr *> &Uses,
94 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
100 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 82 static bool isVectorPredicated(MachineInstr *MI) { in isVectorPredicated()
87 static bool isVectorPredicate(MachineInstr *MI) { in isVectorPredicate()
91 static bool hasVPRUse(MachineInstr &MI) { in hasVPRUse()
95 static bool isDomainMVE(MachineInstr *MI) { in isDomainMVE()
100 static bool shouldInspect(MachineInstr &MI) { in shouldInspect()
104 static bool isDo(MachineInstr *MI) { in isDo()
110 using InstSet = SmallPtrSetImpl<MachineInstr *>;
167 MachineInstr *MI = nullptr;
168 SetVector<MachineInstr*> Predicates;
171 PredicatedMI(MachineInstr *I, SetVector<MachineInstr *> &Preds) : MI(I) { in PredicatedMI()
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| H A D | ARMBaseInstrInfo.h | 61 const MachineInstr &MI, unsigned DefIdx,
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
101 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
108 isCopyInstrImpl(const MachineInstr &MI) const override;
112 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
123 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
124 MachineInstr &MI,
158 bool isPredicated(const MachineInstr &MI) const override;
162 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.h | 180 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
182 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
184 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
186 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
188 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
190 void expandLoadStackGuard(MachineInstr *MI) const;
212 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
220 unsigned isLoadFromStackSlot(const MachineInstr &MI,
222 unsigned isStoreToStackSlot(const MachineInstr &MI,
224 bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 81 static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) { in getMFIfAvailable()
90 static void tryToGetTargetInfo(const MachineInstr &MI, in tryToGetTargetInfo()
104 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { in addImplicitDefUseOperands()
118 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, in MachineInstr() function in MachineInstr
137 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) in MachineInstr() function in MachineInstr
153 void MachineInstr::moveBefore(MachineInstr *MovePos) { in moveBefore()
160 MachineRegisterInfo *MachineInstr::getRegInfo() { in getRegInfo()
169 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { in RemoveRegOperandsFromUseLists()
178 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { in AddRegOperandsToUseLists()
184 void MachineInstr::addOperand(const MachineOperand &Op) { in addOperand()
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