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Searched refs:MVT (Results 1 – 25 of 260) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); in getArithmeticInstrCost()
210 { ISD::FDIV, MVT::f32, 18 }, // divss in getArithmeticInstrCost()
211 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
212 { ISD::FDIV, MVT::f64, 33 }, // divsd in getArithmeticInstrCost()
213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd in getArithmeticInstrCost()
222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld in getArithmeticInstrCost()
223 { ISD::MUL, MVT::v8i16, 2 }, // pmullw in getArithmeticInstrCost()
224 { ISD::FMUL, MVT::f64, 2 }, // mulsd in getArithmeticInstrCost()
225 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd in getArithmeticInstrCost()
226 { ISD::FMUL, MVT::v4f32, 2 }, // mulps in getArithmeticInstrCost()
[all …]
H A DX86ISelLowering.cpp119 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0)); in X86TargetLowering()
182 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
183 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
184 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
186 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
188 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering()
189 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
192 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in X86TargetLowering()
193 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in X86TargetLowering()
194 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); in X86TargetLowering()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h30 class MVT {
306 constexpr MVT() = default;
307 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() function
309 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
310 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
311 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
312 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
313 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
314 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
318 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DValueTypes.cpp164 case MVT::bf16: return "bf16"; in getEVTString()
165 case MVT::ppcf128: return "ppcf128"; in getEVTString()
166 case MVT::isVoid: return "isVoid"; in getEVTString()
167 case MVT::Other: return "ch"; in getEVTString()
168 case MVT::Glue: return "glue"; in getEVTString()
169 case MVT::x86mmx: return "x86mmx"; in getEVTString()
170 case MVT::x86amx: return "x86amx"; in getEVTString()
171 case MVT::Metadata: return "Metadata"; in getEVTString()
172 case MVT::Untyped: return "Untyped"; in getEVTString()
173 case MVT::funcref: return "funcref"; in getEVTString()
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H A DTargetLoweringBase.cpp217 if (OpVT == MVT::f16) { in getFPEXT()
218 if (RetVT == MVT::f32) in getFPEXT()
220 if (RetVT == MVT::f64) in getFPEXT()
222 if (RetVT == MVT::f128) in getFPEXT()
224 } else if (OpVT == MVT::f32) { in getFPEXT()
225 if (RetVT == MVT::f64) in getFPEXT()
227 if (RetVT == MVT::f128) in getFPEXT()
229 if (RetVT == MVT::ppcf128) in getFPEXT()
231 } else if (OpVT == MVT::f64) { in getFPEXT()
232 if (RetVT == MVT::f128) in getFPEXT()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp227 if (LT.second == MVT::v2i64) in getIntrinsicInstrCost()
233 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
234 MVT::v8i16, MVT::v2i32, MVT::v4i32}; in getIntrinsicInstrCost()
236 if (any_of(ValidMinMaxTys, [&LT](MVT M) { return M == LT.second; })) in getIntrinsicInstrCost()
244 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
245 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
246 MVT::v2i64}; in getIntrinsicInstrCost()
252 if (any_of(ValidSatTys, [&LT](MVT M) { return M == LT.second; })) in getIntrinsicInstrCost()
257 static const auto ValidAbsTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
258 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
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H A DAArch64ISelDAGToDAG.cpp184 template<MVT::SimpleValueType VT>
189 template <MVT::SimpleValueType VT, bool Invert = false>
194 template <MVT::SimpleValueType VT>
219 Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32); in SelectCntImm()
327 bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);
329 bool SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm, bool Invert);
335 bool SelectSVEArithImm(SDValue N, MVT VT, SDValue &Imm);
381 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64); in SelectInlineAsmMemoryOperand()
418 Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32); in SelectArithImmed()
419 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32); in SelectArithImmed()
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H A DAArch64FastISel.cpp182 bool isTypeLegal(Type *Ty, MVT &VT);
183 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
187 bool simplifyAddress(Address &Addr, MVT VT);
196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
201 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
204 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
207 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
214 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
222 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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H A DAArch64CallingConvention.h19 bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
22 bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
25 bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
28 bool CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
31 bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
34 bool CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
37 bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT,
40 bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
43 bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
46 bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT,
H A DAArch64ISelLowering.cpp127 static const MVT MVT_CC = MVT::i32;
133 case MVT::i8: in getPackedSVEVectorVT()
134 return MVT::nxv16i8; in getPackedSVEVectorVT()
135 case MVT::i16: in getPackedSVEVectorVT()
136 return MVT::nxv8i16; in getPackedSVEVectorVT()
137 case MVT::i32: in getPackedSVEVectorVT()
138 return MVT::nxv4i32; in getPackedSVEVectorVT()
139 case MVT::i64: in getPackedSVEVectorVT()
140 return MVT::nxv2i64; in getPackedSVEVectorVT()
141 case MVT::f16: in getPackedSVEVectorVT()
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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenTarget.cpp45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { in getValueType()
46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); in getValueType()
49 StringRef llvm::getName(MVT::SimpleValueType T) { in getName()
51 case MVT::Other: return "UNKNOWN"; in getName()
52 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
53 case MVT::iPTRAny: return "TLI.getPointerTy()"; in getName()
58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { in getEnumName()
60 case MVT::Other: return "MVT::Other"; in getEnumName()
61 case MVT::i1: return "MVT::i1"; in getEnumName()
62 case MVT::i8: return "MVT::i8"; in getEnumName()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp412 return (EltVT == MVT::f32 && ST->hasVFP2Base()) || in getCastInstrCost()
413 (EltVT == MVT::f64 && ST->hasFP64()) || in getCastInstrCost()
414 (EltVT == MVT::f16 && ST->hasFullFP16()); in getCastInstrCost()
441 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
442 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
443 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
444 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
445 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
446 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
447 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
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H A DARMCallingConv.h20 bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
23 bool CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
26 bool CC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
29 bool CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
32 bool FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
35 bool CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
38 bool RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
41 bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
44 bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
47 bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp21 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
22 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
23 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
24 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
30 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
31 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
32 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
33 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
34 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
35 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
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H A DHexagonISelLowering.cpp137 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_SkipOdd()
174 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
257 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
365 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
373 MVT::i32, Glue); in LowerCallResult()
382 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
420 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32); in LowerCall()
498 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); in LowerCall()
531 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
583 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp44 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
66 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
67 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
69 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
70 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
72 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
73 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
75 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
76 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
78 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
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H A DR600ISelLowering.cpp31 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
32 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
33 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
44 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
45 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
46 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
50 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
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H A DSIISelLowering.cpp78 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
79 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
81 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
82 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
84 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
89 addRegisterClass(MVT::f64, V64RegClass); in SITargetLowering()
90 addRegisterClass(MVT::v2f32, V64RegClass); in SITargetLowering()
92 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass); in SITargetLowering()
93 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering()
95 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass); in SITargetLowering()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp85 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in ExpandMI()
87 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in ExpandMI()
89 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in ExpandMI()
92 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in ExpandMI()
94 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in ExpandMI()
96 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in ExpandMI()
99 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8); in ExpandMI()
101 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i8); in ExpandMI()
103 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16); in ExpandMI()
106 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i16, in ExpandMI()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp41 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
42 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
54 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Split_64()
55 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Split_64()
80 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Ret_Split_64()
81 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Ret_Split_64()
104 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Full()
105 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Full()
107 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
112 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp118 MVT::SimpleValueType getSimpleType(Type *Ty) { in getSimpleType()
121 : MVT::INVALID_SIMPLE_VALUE_TYPE; in getSimpleType()
123 MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) { in getLegalType()
125 case MVT::i1: in getLegalType()
126 case MVT::i8: in getLegalType()
127 case MVT::i16: in getLegalType()
128 return MVT::i32; in getLegalType()
129 case MVT::i32: in getLegalType()
130 case MVT::i64: in getLegalType()
131 case MVT::f32: in getLegalType()
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H A DWebAssemblyISelLowering.cpp45 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; in WebAssemblyTargetLowering()
57 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
58 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
59 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
60 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
62 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
63 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
64 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
65 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
66 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp61 MVT WebAssembly::parseMVT(StringRef Type) { in parseMVT()
62 return StringSwitch<MVT>(Type) in parseMVT()
63 .Case("i32", MVT::i32) in parseMVT()
64 .Case("i64", MVT::i64) in parseMVT()
65 .Case("f32", MVT::f32) in parseMVT()
66 .Case("f64", MVT::f64) in parseMVT()
67 .Case("i64", MVT::i64) in parseMVT()
68 .Case("v16i8", MVT::v16i8) in parseMVT()
69 .Case("v8i16", MVT::v8i16) in parseMVT()
70 .Case("v4i32", MVT::v4i32) in parseMVT()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp149 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
152 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
155 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
157 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
158 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
163 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
164 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
167 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); in PPCTargetLowering()
170 setOperationAction(ISD::INLINEASM, MVT::Other, Custom); in PPCTargetLowering()
171 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); in PPCTargetLowering()
[all …]
H A DPPCFastISel.cpp112 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
141 bool isTypeLegal(Type *Ty, MVT &VT);
142 bool isLoadTypeLegal(Type *Ty, MVT &VT);
161 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
164 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
168 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
170 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
171 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
172 unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
178 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
[all …]

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