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Searched refs:MRI (Results 1 – 25 of 686) sorted by relevance

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/netbsd-src/external/gpl3/binutils/dist/ld/
H A Dldlex.l107 %s MRI
133 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ {
139 <MRI,EXPRESSION>([0-9A-Fa-f])+(H|h|X|x|B|b|O|o|D|d) {
163 <SCRIPT,MRI,EXPRESSION>((("$"|0[xX])([0-9A-Fa-f])+)|(([0-9])+))(M|K|m|k)? {
216 <MRI,WILD>"]" { RTOKEN(']'); }
217 <MRI,WILD>"[" { RTOKEN('['); }
218 <SCRIPT,EXPRESSION,MRI,WILD>"<<=" { RTOKEN(LSHIFTEQ); }
219 <SCRIPT,EXPRESSION,MRI,WILD>">>=" { RTOKEN(RSHIFTEQ); }
220 <EXPRESSION,MRI>"||" { RTOKEN(OROR); }
221 <EXPRESSION,MRI>"==" { RTOKEN(EQ); }
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/ld/
H A Dldlex.l107 %s MRI
133 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ {
139 <MRI,EXPRESSION>([0-9A-Fa-f])+(H|h|X|x|B|b|O|o|D|d) {
164 <SCRIPT,MRI,EXPRESSION>((("$"|0[xX])([0-9A-Fa-f])+)|(([0-9])+))(M|K|m|k)? {
217 <MRI,WILD>"]" { RTOKEN(']'); }
218 <MRI,WILD>"[" { RTOKEN('['); }
219 <SCRIPT,EXPRESSION,MRI,WILD>"<<=" { RTOKEN(LSHIFTEQ); }
220 <SCRIPT,EXPRESSION,MRI,WILD>">>=" { RTOKEN(RSHIFTEQ); }
221 <EXPRESSION,MRI>"||" { RTOKEN(OROR); }
222 <EXPRESSION,MRI>"==" { RTOKEN(EQ); }
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
45 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
60 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
62 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
H A DAMDGPURegisterBankInfo.cpp100 MachineRegisterInfo &MRI; member in __anonb6f5fc490111::ApplyRegBankMapping
107 : RBI(RBI_), MRI(MRI_), NewBank(RB) {} in ApplyRegBankMapping()
124 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
127 assert(MRI.getType(SrcReg) == LLT::scalar(1)); in applyBank()
128 assert(MRI.getType(DstReg) == S32); in applyBank()
137 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
138 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
142 assert(!MRI.getRegClassOrRegBank(DstReg)); in applyBank()
143 MRI.setRegBank(DstReg, *NewBank); in applyBank()
150 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
[all …]
H A DAMDGPUInstructionSelector.cpp67 MRI = &MF.getRegInfo(); in setupMF()
73 const MachineRegisterInfo &MRI) const { in isVCC()
78 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); in isVCC()
82 const LLT Ty = MRI.getType(Reg); in isVCC()
101 if (MRI->getType(Dst.getReg()) == LLT::scalar(1)) in constrainCopyLikeIntrin()
105 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in constrainCopyLikeIntrin()
107 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in constrainCopyLikeIntrin()
111 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
112 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
125 if (isVCC(DstReg, *MRI)) { in selectCOPY()
[all …]
H A DGCNRegPressure.cpp25 const MachineRegisterInfo &MRI) { in printLivesAt() argument
29 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { in printLivesAt()
39 dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo()) in printLivesAt()
73 const MachineRegisterInfo &MRI) { in getRegKind() argument
75 const auto RC = MRI.getRegClass(Reg); in getRegKind()
76 auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo()); in getRegKind()
87 const MachineRegisterInfo &MRI) { in inc() argument
98 switch (auto Kind = getRegKind(Reg, MRI)) { in inc()
115 Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight(); in inc()
188 const MachineRegisterInfo &MRI) { in getDefRegMask() argument
[all …]
H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
77 MachineRegisterInfo &MRI) const;
81 MachineRegisterInfo &MRI, int RSrcIdx) const;
87 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
99 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI,
[all …]
H A DSIFixSGPRCopies.cpp91 MachineRegisterInfo *MRI; member in __anonc6b6fc400111::SIFixSGPRCopies
129 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasVectorOperands() local
134 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
143 const MachineRegisterInfo &MRI) { in getCopyRegClasses() argument
148 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
155 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
178 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in tryChangeVGPRtoSGPRinCopy() local
185 for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) { in tryChangeVGPRtoSGPRinCopy()
199 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
219 MachineRegisterInfo &MRI) { in foldVGPRCopyIntoRegSequence() argument
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp52 MachineRegisterInfo &MRI) { in IsRegInClass()
54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
62 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
63 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
66 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
67 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
70 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
71 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
74 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
75 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
[all …]
H A DPPCMIPeephole.cpp89 MachineRegisterInfo *MRI; member
144 MRI = &MF->getRegInfo(); in initialize()
155 MachineRegisterInfo *MRI) { in getVRegDefOrNull() argument
164 return MRI->getVRegDef(Reg); in getVRegDefOrNull()
278 static bool collectUnprimedAccPHIs(MachineRegisterInfo *MRI, in collectUnprimedAccPHIs() argument
290 MachineInstr *Instr = MRI->getVRegDef(RegOp); in collectUnprimedAccPHIs()
297 MRI->getRegClass(Reg) != &PPC::ACCRCRegClass) in collectUnprimedAccPHIs()
321 MachineRegisterInfo *MRI, in convertUnprimedAccPHIs() argument
335 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); in convertUnprimedAccPHIs()
341 assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) == in convertUnprimedAccPHIs()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp77 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
79 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
81 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
83 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
85 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
87 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
89 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
91 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
93 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
95 bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp66 MachineRegisterInfo *MRI; member in __anon05f755c70111::AArch64AdvSIMDScalar
105 const MachineRegisterInfo *MRI) { in isGPR64() argument
109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
114 const MachineRegisterInfo *MRI) { in isFPR64() argument
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
128 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
145 MRI) && in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
149 MRI) && in getSrcFromCopy()
[all …]
H A DAArch64Combine.td17 [{ return matchFConstantToConstant(*${root}, MRI); }]),
24 [{ return matchICmpRedundantTrunc(*${root}, MRI, Helper.getKnownBits(), ${matchinfo}); }]),
25 (apply [{ applyICmpRedundantTrunc(*${root}, MRI, B, Observer, ${matchinfo}); }])>;
32 [{ return matchFoldGlobalOffset(*${root}, MRI, ${matchinfo}); }]),
33 (apply [{ return applyFoldGlobalOffset(*${root}, MRI, B, Observer, ${matchinfo});}])
60 [{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
67 [{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
74 [{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
81 [{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
88 [{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp38 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass() argument
42 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
43 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
50 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
57 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
83 MachineInstr *RegDef = MRI.getVRegDef(Reg); in constrainOperandRegClass()
86 Observer->changingAllUsesOfReg(MRI, Reg); in constrainOperandRegClass()
95 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
112 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
130 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
[all …]
H A DCombinerHelper.cpp47 : Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer), in CombinerHelper()
121 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, in replaceRegWith() argument
123 Observer.changingAllUsesOfReg(MRI, FromReg); in replaceRegWith()
125 if (MRI.constrainRegAttrs(ToReg, FromReg)) in replaceRegWith()
126 MRI.replaceRegWith(FromReg, ToReg); in replaceRegWith()
133 void CombinerHelper::replaceRegOpWith(MachineRegisterInfo &MRI, in replaceRegOpWith() argument
156 return canReplaceReg(DstReg, SrcReg, MRI); in matchCombineCopy()
162 replaceRegWith(MRI, DstReg, SrcReg); in applyCombineCopy()
187 MachineInstr *Def = MRI.getVRegDef(Reg); in matchCombineConcatVectors()
198 LLT OpType = MRI.getType(Reg); in matchCombineConcatVectors()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp104 bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI);
108 MachineRegisterInfo &MRI);
110 bool convertPtrAddToAdd(MachineInstr &I, MachineRegisterInfo &MRI);
113 MachineRegisterInfo &MRI) const;
115 MachineRegisterInfo &MRI) const;
131 MachineRegisterInfo &MRI);
133 bool selectVectorAshrLshr(MachineInstr &I, MachineRegisterInfo &MRI);
134 bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI);
161 MachineRegisterInfo &MRI);
163 bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI);
[all …]
H A DAArch64PostLegalizerLowering.cpp218 static bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI, in matchREV() argument
224 LLT Ty = MRI.getType(Dst); in matchREV()
247 static bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI, in matchTRN() argument
253 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchTRN()
268 static bool matchUZP(MachineInstr &MI, MachineRegisterInfo &MRI, in matchUZP() argument
274 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchUZP()
284 static bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI, in matchZip() argument
290 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchZip()
302 MachineRegisterInfo &MRI, in matchDupFromInsertVectorElt() argument
322 MI.getOperand(1).getReg(), MRI); in matchDupFromInsertVectorElt()
[all …]
H A DAArch64RegisterBankInfo.cpp287 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings() local
293 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
314 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
350 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
436 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getSameKindOfOperandsMapping() local
442 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameKindOfOperandsMapping()
458 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg()); in getSameKindOfOperandsMapping()
486 const MachineRegisterInfo &MRI, in hasFPConstraints() argument
504 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
519 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints()
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H A DAArch64PostLegalizerCombiner.cpp51 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd() argument
55 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchExtractVecEltPairwiseAdd()
57 auto Cst = getConstantVRegValWithLookThrough(Src2, MRI); in matchExtractVecEltPairwiseAdd()
63 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI); in matchExtractVecEltPairwiseAdd()
75 getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI); in matchExtractVecEltPairwiseAdd()
76 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd()
78 Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI); in matchExtractVecEltPairwiseAdd()
79 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd()
84 Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) { in matchExtractVecEltPairwiseAdd()
94 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyExtractVecEltPairwiseAdd() argument
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h24 bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P) { in mi_match() argument
25 return P.match(MRI, R); in mi_match()
29 bool mi_match(MachineInstr &MI, const MachineRegisterInfo &MRI, Pattern &&P) { in mi_match() argument
30 return P.match(MRI, &MI); in mi_match()
38 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
39 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); in match()
52 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
53 return MRI.hasOneNonDBGUse(Reg) && SubPat.match(MRI, Reg); in match()
65 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
66 if (auto MaybeCst = getConstantVRegSExtVal(Reg, MRI)) { in match()
[all …]
H A DUtils.h85 Register constrainRegToClass(MachineRegisterInfo &MRI,
100 MachineRegisterInfo &MRI,
119 MachineRegisterInfo &MRI,
141 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
145 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
166 const MachineRegisterInfo &MRI);
171 const MachineRegisterInfo &MRI);
189 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
194 const MachineRegisterInfo &MRI);
196 const MachineRegisterInfo &MRI);
[all …]
H A DLegalizationArtifactCombiner.h31 MachineRegisterInfo &MRI; variable
47 LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI, in LegalizationArtifactCombiner() argument
49 : Builder(B), MRI(MRI), LI(LI) {} in LegalizationArtifactCombiner()
62 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineAnyExt()
66 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt()
73 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
84 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt()
86 const LLT DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
113 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc))) || in tryCombineZExt()
114 mi_match(SrcReg, MRI, m_GSExt(m_Reg(SextSrc)))) { in tryCombineZExt()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp59 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
62 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
65 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
67 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
69 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
91 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr() argument
100 auto Begin = MRI->use_begin(Op0.getReg()), End = MRI->use_end(); in checkADDrr()
105 if (!MRI->getUniqueVRegDef(I->getReg())) in checkADDrr()
145 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift() argument
159 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate() argument
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp48 MachineRegisterInfo &MRI) const;
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
186 MachineRegisterInfo &MRI, in guessRegClass() argument
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
192 const unsigned Size = MRI.getType(Reg).getSizeInBits(); in guessRegClass()
212 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy() argument
218 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DModuloSchedule.cpp84 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(Reg), in expand()
85 EI = MRI.use_end(); in expand()
335 MachineRegisterInfo &MRI, in replaceRegUsesAfterLoop() argument
337 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(FromReg), in replaceRegUsesAfterLoop()
338 E = MRI.use_end(); in replaceRegUsesAfterLoop()
352 MachineRegisterInfo &MRI) { in hasUseAfterLoop() argument
353 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg), in hasUseAfterLoop()
354 E = MRI.use_end(); in hasUseAfterLoop()
399 int LoopValStage = Schedule.getStage(MRI.getVRegDef(LoopVal)); in generateExistingPhis()
450 MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1); in generateExistingPhis()
[all …]

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