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Searched refs:MM0 (Results 1 – 13 of 13) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86Instr3DNow.td77 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
H A DX86CallingConv.td251 // MMX vector types are always returned in MM0. If the target doesn't have
252 // MM0, it doesn't support these vector types.
253 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
821 CCAssignToReg<[MM0, MM1, MM2]>>>,
H A DX86InstrMMX.td152 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
H A DX86RegisterInfo.td192 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
H A DX86InstrCompiler.td452 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
472 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h206 ENTRY(MM0) \
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp123 {codeview::RegisterId::MM0, X86::MM0}, in initLLVMToSEHAndCVRegMapping()
H A DX86InstComments.cpp243 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def143 CV_REGISTER(MM0, 146)
/netbsd-src/external/apache2/llvm/dist/llvm/docs/TableGen/
H A Dindex.rst69 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
H A DProgRef.rst860 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DInstructionSimplify.cpp5371 auto *MM0 = dyn_cast<IntrinsicInst>(Op0); in foldMinMaxSharedOp() local
5372 if (!MM0) in foldMinMaxSharedOp()
5374 Intrinsic::ID IID0 = MM0->getIntrinsicID(); in foldMinMaxSharedOp()
5380 return MM0; in foldMinMaxSharedOp()
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DCodeGenerator.rst1244 ``EAX`` is denoted by 43, and the MMX register ``MM0`` is mapped to 65.