| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | MIRLangRef.rst | 2 Machine IR (MIR) Format Reference Manual 14 This document is a reference manual for the Machine IR (MIR) serialization 15 format. MIR is a human readable serialization format that is used to represent 19 The MIR serialization format is designed to be used for testing the code 25 The MIR serialization format uses a YAML container. YAML is a standard 30 A MIR file is split up into a series of `YAML documents`_. The first document 36 MIR Testing Guide 39 You can use the MIR format for testing in two different ways: 41 - You can write MIR tests that invoke a single code generation pass using the 45 tests and check the MIR output of a specific code generation pass. [all …]
|
| H A D | Reference.rst | 121 :doc:`Machine IR (MIR) Format Reference Manual <MIRLangRef>` 122 A reference manual for the MIR serialization format, which is used to test
|
| H A D | HowToUpdateDebugInfo.rst | 215 Deleting a MIR-level MachineInstr 331 There is also a MIR-level debugify pass that can be run before each backend 333 :ref:`Mutation testing for MIR-level transformations<MIRDebugify>`. 393 Mutation testing for MIR-level transformations 398 for MIR-level transformations as well: much like the IR-level pass, 400 ``MachineInstr`` in a ``Module``. And the MIR-level ``mir-check-debugify`` is
|
| H A D | SourceLevelDebugging.rst | 552 Variable locations in Instruction Selection and MIR 555 Instruction selection creates a MIR function from an IR function, and just as 558 Within IR, variable locations are always identified by a Value, but in MIR 567 has occurred and a MIR function is created, if the SDNode associated with debug 574 in IR the location would be assigned ``undef`` by a debug intrinsic, and in MIR 577 After MIR locations are assigned to each variable, machine pseudo-instructions 652 …codegen-prepare -stop-after=expand-isel-pseudos -mtriple=x86_64--``, the following MIR is produced: 712 of the delay. To illustrate, consider this pseudo-MIR: 723 Imagine that the SUB32rr were moved forward to give us the following MIR: 734 In this circumstance LLVM would leave the MIR as shown above. Were we to move [all …]
|
| H A D | NewPassManager.rst | 370 they are LLVM IR passes (whereas all MIR passes are codegen passes). This
|
| H A D | AMDGPUUsage.rst | 2006 The AMDGPU backend may generate the following pseudo LLVM MIR to manipulate the 2049 description of a vector of lane program locations, the LLVM MIR ``DBG_VALUE`` 2076 The following provides an example using pseudo LLVM MIR.
|
| H A D | LangRef.rst | 5521 - ``DW_OP_LLVM_entry_value, N`` may only appear in MIR and at the
|
| /netbsd-src/external/apache2/llvm/dist/llvm/utils/vim/syntax/ |
| H A D | mir.vim | 14 " MIR is embedded in a yaml container, so we load all of the yaml syntax. 24 " The `body:` field of a document contains the MIR dump of the function 25 syntax include @MIR syntax/machine-ir.vim 26 syntax region mir start=/\(^body:\s*|\)\@<=/ end=/\(^[^[:space:]]\)\@=/ contains=@MIR
|
| H A D | machine-ir.vim | 8 " FIXME: MIR doesn't actually match LLVM IR. Stop including it all as a 10 " See the MIR LangRef: https://llvm.org/docs/MIRLangRef.html
|
| /netbsd-src/external/apache2/llvm/dist/llvm/docs/GlobalISel/ |
| H A D | Pipeline.rst | 22 Converts :doc:`LLVM-IR <../LangRef>` into :doc:`gMIR (Generic MIR) <GMIR>`. 24 It's somewhat analogous to SelectionDAGBuilder but builds a flavour of MIR 26 same data structures as MIR but has more relaxed constraints. For example, 35 can shape the MIR as they wish. 40 cross-register-bank copies by clustering portions of the MIR together. 45 constrained enough that it becomes MIR. 56 The representation must be gMIR, MIR, or a mixture of the two after this pass. 58 gradually transition the gMIR to MIR. 71 have completed the conversion from gMIR to MIR. 135 and perform a single step of the algorithm and check the result. The MIR and
|
| H A D | GMIR.rst | 9 Generic MIR (gMIR) is an intermediate representation that shares the same data 10 structures as :doc:`MachineIR (MIR) <../MIRLangRef>` but has more relaxed 12 gradually tightened until gMIR has become MIR. 15 in :doc:`MachineIR (MIR) <../MIRLangRef>` and will highlight the differences 16 between MIR and gMIR. 25 This section expands on :ref:`mir-instructions` from the MIR Language 28 Whereas MIR deals largely in Target Instructions and only has a small set of 46 This section expands on :ref:`mir-registers` from the MIR Language
|
| H A D | Porting.rst | 15 * :ref:`InstructionSelector <api-instructionselector>` --- select generic MIR 16 to target-specific MIR.
|
| H A D | index.rst | 18 Machine IR (MIR). 27 rest of the code generator, MIR. 79 SelectionDAG, FastISel, or the other MIR passes. For instance, the types of
|
| H A D | InstructionSelect.rst | 74 ensure the target pseudo is introduced to the MIR before the instruction 94 * Don't modify MIR in the predicate
|
| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llc/ |
| H A D | llc.cpp | 430 std::unique_ptr<MIRParser> MIR; in compileModule() local 524 MIR = createMIRParserFromFile(InputFilename, Err, Context, in compileModule() 526 if (MIR) in compileModule() 527 M = MIR->parseIRModule(SetDataLayout); in compileModule() 635 if (!MIR) { in compileModule() 667 if (MIR) { in compileModule() 669 if (MIR->parseMachineFunctions(*M, MMIWP->getMMI())) in compileModule()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86PreTileConfig.cpp | 201 MIRef MIR(MI, MBB); in INITIALIZE_PASS_DEPENDENCY() local 202 auto I = llvm::lower_bound(ShapeBBs[MBB], MIR); in INITIALIZE_PASS_DEPENDENCY() 203 if (I == ShapeBBs[MBB].end() || *I != MIR) in INITIALIZE_PASS_DEPENDENCY() 204 ShapeBBs[MBB].insert(I, MIR); in INITIALIZE_PASS_DEPENDENCY()
|
| /netbsd-src/sys/dev/pci/ |
| H A D | oboe.c | 719 SPEEDCASE(1152000, MIR, 0x01); in oboe_setbaud()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/GlobalISel/ |
| H A D | Combine.td | 96 /// * A MIR code block (deprecated) 111 /// sub-dags whose operator is GIApplyKindWithArgs, or an MIR block
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 3555 // cause iterator invalidation in MIR transformation passes, this pseudo can be
|
| /netbsd-src/share/misc/ |
| H A D | airport | 4743 MIR:Monastir (Skanes), Tunisia
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/ |
| H A D | ChangeLog-2015 | 11785 using the MIR dataflow problem. Update the call to
|