| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 197 MachineInstr *MI2 = nullptr,
398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
403 if (!GetImm(MI2, 2, Offset2)) in ConsecutiveInstr()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
465 MachineInstr *MI2 = &*NextMII; in ReduceXWtoXWP() local
475 if (!CheckXWPInstr(MI2, ReduceToLwp, Entry)) in ReduceXWtoXWP()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP()
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
485 bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1); in ReduceXWtoXWP()
491 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward); in ReduceXWtoXWP()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFMIPeephole.cpp | 462 MachineInstr *MI2 = nullptr; in eliminateTruncSeq() local
481 MI2 = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
484 if (!MI2 || in eliminateTruncSeq()
485 MI2->getOpcode() != BPF::SLL_ri || in eliminateTruncSeq()
486 MI2->getOperand(2).getImm() != 32) in eliminateTruncSeq()
490 SrcReg = MI2->getOperand(1).getReg(); in eliminateTruncSeq()
541 if (MI2) in eliminateTruncSeq()
542 MI2->eraseFromParent(); in eliminateTruncSeq()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 431 MachineInstr *MI2 = *I2; in hoistAndMergeSGPRInits() local
466 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
467 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
470 << printMBBReference(*MI2->getParent()) << " " << *MI2); in hoistAndMergeSGPRInits()
471 MergedInstrs.insert(MI2); in hoistAndMergeSGPRInits()
476 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
477 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
488 MI2->getParent()); in hoistAndMergeSGPRInits()
495 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
500 << printMBBReference(*MI2->getParent()) << " to " in hoistAndMergeSGPRInits()
[all …]
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| H A D | SIInstrInfo.cpp | 398 const MachineInstr &MI2, in memOpsHaveSameBasePtr() argument
406 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
410 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 302 const MachineInstr &MI2, in alias() argument
304 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias()
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| H A D | TargetInstrInfo.cpp | 709 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
713 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
716 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
724 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
729 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
731 std::swap(MI1, MI2); in hasReassociableSibling()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 225 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply() local
226 if (!QII->isHVXVec(MI2)) in apply()
228 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) { in apply()
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| H A D | HexagonInstrInfo.h | 402 const MachineInstr &MI2) const;
414 const MachineInstr &MI2) const;
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| H A D | HexagonVLIWPacketizer.h | 141 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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| H A D | HexagonVLIWPacketizer.cpp | 968 MachineInstr &MI2) { in arePredicatesComplements() argument
972 getPredicateSense(MI2, HII) == PK_Unknown) in arePredicatesComplements()
1025 unsigned PReg2 = getPredicatedRegister(MI2, HII); in arePredicatesComplements()
1029 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1030 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
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| H A D | HexagonInstrInfo.cpp | 2644 const MachineInstr &MI2) const { in isToBeScheduledASAP()
2648 int N = MI2.getNumOperands(); in isToBeScheduledASAP()
2650 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg()) in isToBeScheduledASAP()
2653 if (mayBeNewStore(MI2)) in isToBeScheduledASAP()
2654 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi) in isToBeScheduledASAP()
2655 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2656 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
2965 const MachineInstr &MI2) const { in addLatencyToSchedule()
2966 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
2967 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
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| H A D | HexagonPatterns.td | 817 class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
819 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 278 const MachineInstr &MI2, unsigned N2) const;
401 const MachineInstr &MI2, in getAddrDispShift() argument
404 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
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| H A D | X86ISelLowering.h | 1608 MachineInstr &MI2,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 314 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
318 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | DFAPacketizer.h | 190 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 1444 auto MI2 = in expand() local
1450 MI2->getOperand(3).setIsDead(); in expand()
1604 auto MI2 = in expand() local
1610 MI2->getOperand(3).setIsDead(); in expand()
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| /netbsd-src/external/gpl3/gdb.old/dist/gdb/ |
| H A D | ChangeLog-2007 | 3953 * mi-main.c (mi_load_progress): Handle MI2 and MI3 interpreters.
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| /netbsd-src/external/gpl3/gdb/dist/gdb/ |
| H A D | ChangeLog-2007 | 3953 * mi-main.c (mi_load_progress): Handle MI2 and MI3 interpreters.
|