Searched refs:MFENCE (Results 1 – 13 of 13) sorted by relevance
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/ |
| H A D | sync.md | 237 /* For seq-cst stores, use XCHG when we lack MFENCE. */
252 /* ... followed by an MFENCE, if required. */
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/ |
| H A D | sync.md | 244 /* For seq-cst stores, use XCHG when we lack MFENCE. */
259 /* ... followed by an MFENCE, if required. */
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 386 if (MI.getOpcode() == X86::MFENCE) in hasVulnerableLoad()
1318 if (MI.getOpcode() == X86::MFENCE) in tracePredStateThroughBlocksAndHarden()
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| H A D | X86LoadValueInjectionLoadHardening.cpp | 771 if (!MI.mayLoadOrStore() || MI.getOpcode() == X86::MFENCE || in instrUsesRegToAccessMemory()
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| H A D | X86ISelLowering.h | 648 MFENCE, enumerator
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| H A D | X86SchedBroadwell.td | 703 MFENCE,
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| H A D | X86SchedSkylakeClient.td | 825 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
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| H A D | X86SchedHaswell.td | 1105 MFENCE,
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| H A D | X86SchedSkylakeServer.td | 894 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
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| H A D | X86InstrSSE.td | 3201 def MFENCE : I<0xAE, MRM6X, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>,
3205 def : Pat<(X86MFence), (MFENCE)>;
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| H A D | X86InstrInfo.td | 137 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
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| H A D | X86ISelLowering.cpp | 29195 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); in LowerATOMIC_FENCE()
31500 NODE_NAME_CASE(MFENCE) in getTargetNodeName()
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | Atomics.rst | 438 fences generate an ``MFENCE``, other fences do not cause any code to be
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