Searched refs:MCRegisterClass (Results 1 – 17 of 17) sorted by relevance
66 const MCRegisterClass *GPR32RegClass;67 const MCRegisterClass *GPR64RegClass;68 const MCRegisterClass *FGR32RegClass;69 const MCRegisterClass *FGR64RegClass;70 const MCRegisterClass *AFGR64RegClass;71 const MCRegisterClass *MSA128BRegClass;72 const MCRegisterClass *COP0RegClass;73 const MCRegisterClass *COP2RegClass;74 const MCRegisterClass *COP3RegClass;
31 class MCRegisterClass {137 using regclass_iterator = const MCRegisterClass *;160 const MCRegisterClass *Classes; // Pointer to the regclass array355 const MCRegisterClass *C, unsigned NC, in InitMCRegisterInfo()466 const MCRegisterClass *RC) const;543 const MCRegisterClass& getRegClass(unsigned i) const { in getRegClass()548 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName()
45 const MCRegisterClass &RegClass);
33 const MCRegisterClass &RegClass) in RegisterAliasingTracker()
25 const MCRegisterClass *RC) const { in getMatchingSuperReg()
107 const MCRegisterClass *GPR64RegClass = in hasLiveDefs()
25 class MCRegisterClass; variable772 unsigned getRegBitWidth(const MCRegisterClass &RC);
1467 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID); in isSGPR()1675 unsigned getRegBitWidth(const MCRegisterClass &RC) { in getRegBitWidth()
428 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); in clearsSuperRegisters()429 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); in clearsSuperRegisters()430 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); in clearsSuperRegisters()
53 const MCRegisterClass *MC;
162 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); in addRegisterFile()
78 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID]; in toDREG()
2460 const MCRegisterClass RC = TRI->getRegClass(RCID); in getRegularReg()4051 const MCRegisterClass &AGRP32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in IsAGPROperand()4091 const MCRegisterClass &VGRP32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign()4092 const MCRegisterClass &AGRP32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in validateVGPRAlign()
1306 const MCRegisterClass &FPR128RC = in printVectorList()
262 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); in printInst()
3352 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; in addMVEVecListOperands()3353 const MCRegisterClass *RC_out = (VectorList.Count == 2) ? in addMVEVecListOperands()4493 const MCRegisterClass *RC; in parseRegisterList()4914 const MCRegisterClass *RC = (Spacing == 1) ? in parseVectorList()6952 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias()7409 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
6162 const MCRegisterClass &WRegClass = in tryParseGPRSeqPair()6164 const MCRegisterClass &XRegClass = in tryParseGPRSeqPair()