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Searched refs:MCII (Results 1 – 25 of 91) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
41 : MCII(MCII), BundleCurrent(Inst.begin() + in PacketIterator()
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()), in PacketIterator()
63 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in operator ++()
88 MCInstrInfo const &MCII, MCInst &MCB, in addConstExtender() argument
92 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI)); in addConstExtender()
96 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp)); in addConstExtender()
103 HexagonMCInstrInfo::bundleInstructions(MCInstrInfo const &MCII, in bundleInstructions() argument
106 return make_range(Hexagon::PacketIterator(MCII, MCI), in bundleInstructions()
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H A DHexagonMCInstrInfo.h45 MCInstrInfo const &MCII; variable
52 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
53 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
81 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
86 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
93 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
101 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
109 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
113 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
116 unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI);
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H A DHexagonMCChecker.cpp56 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in init()
68 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { in initReg()
71 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); in initReg()
74 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in initReg()
90 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
123 HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) in init()
165 else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && in init()
169 else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) == in init()
177 else if (i <= 1 && HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) in init()
187 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in init()
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H A DHexagonMCShuffler.cpp39 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) in init()
41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
44 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
59 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
66 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
72 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
105 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument
107 HexagonMCShuffler MCS(Context, Fatal, MCII, STI, MCB); in HexagonMCShuffle()
132 llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
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H A DHexagonShuffler.cpp108 HexagonCVIResource::HexagonCVIResource(MCInstrInfo const &MCII, in HexagonCVIResource() argument
114 const unsigned ItinUnits = HexagonMCInstrInfo::getCVIResources(MCII, STI, *id); in HexagonCVIResource()
130 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
131 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
168 MCInstrInfo const &MCII, in HexagonShuffler() argument
170 : Context(Context), MCII(MCII), STI(STI), ReportErrors(ReportErrors) { in HexagonShuffler()
182 HexagonInstr PI(MCII, STI, &ID, Extender, S); in append()
198 const unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst); in restrictSlot1AOK()
230 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store()
371 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
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H A DHexagonMCShuffler.h31 HexagonMCShuffler(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, in HexagonMCShuffler() argument
33 : HexagonShuffler(Context, Fatal, MCII, STI) { in HexagonMCShuffler()
37 HexagonMCShuffler(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, in HexagonMCShuffler() argument
40 : HexagonShuffler(Context, Fatal, MCII, STI) { in HexagonMCShuffler()
56 bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII,
58 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
61 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
H A DHexagonMCCodeEmitter.cpp342 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
408 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && in EncodeSingleInstruction()
411 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in EncodeSingleInstruction()
420 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in EncodeSingleInstruction()
463 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, in getFixupNoBits() argument
465 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); in getFixupNoBits()
466 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI); in getFixupNoBits()
477 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI); in getFixupNoBits()
479 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR) in getFixupNoBits()
585 bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) || in getExprOpValue()
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H A DHexagonAsmBackend.cpp44 std::unique_ptr <MCInstrInfo> MCII; member in __anond55340020111::HexagonAsmBackend
66 MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
539 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
542 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
543 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && in isInstRelaxable()
545 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ && in isInstRelaxable()
547 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && in isInstRelaxable()
549 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
552 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
675 *MCII, CrntHMI, in relaxInstruction()
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H A DHexagonShuffler.h97 HexagonCVIResource(MCInstrInfo const &MCII,
117 HexagonInstr(MCInstrInfo const &MCII, in HexagonInstr() argument
120 : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; in HexagonInstr()
174 MCInstrInfo const &MCII; variable
203 MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
236 return (*Pred)(MCII, Inst); in HasInstWith()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp37 MCInstrInfo const &MCII; member in llvm::MSP430MCCodeEmitter
74 MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in MSP430MCCodeEmitter() argument
75 : Ctx(ctx), MCII(MCII) {} in MSP430MCCodeEmitter()
85 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
202 MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, in createMSP430MCCodeEmitter() argument
205 return new MSP430MCCodeEmitter(Ctx, MCII); in createMSP430MCCodeEmitter()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp39 const MCInstrInfo &MCII; member in __anon41f9f2e60111::WebAssemblyMCCodeEmitter
51 WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) : MCII(MCII) {} in WebAssemblyMCCodeEmitter() argument
55 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) { in createWebAssemblyMCCodeEmitter() argument
56 return new WebAssemblyMCCodeEmitter(MCII); in createWebAssemblyMCCodeEmitter()
87 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp45 std::unique_ptr<MCInstrInfo const> const MCII; member in __anonb9d40f5f0111::HexagonDisassembler
50 MCInstrInfo const *MCII) in HexagonDisassembler() argument
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), in HexagonDisassembler()
65 MCInstrInfo MCII = *Disassembler.MCII; in fullValue() local
67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) in fullValue()
69 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); in fullValue()
191 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI, in getInstruction()
460 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { in getSingleInstruction()
461 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); in getSingleInstruction()
471 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); in getSingleInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCSchedule.cpp68 const MCInstrInfo &MCII, in computeInstrLatency() argument
70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency()
77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
111 const MCInstrInfo &MCII, in getReciprocalThroughput() argument
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput()
123 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp32 const MCInstrInfo &MCII; member in __anon6b4daf700111::R600MCCodeEmitter
36 : MRI(mri), MCII(mcii) {} in R600MCCodeEmitter()
86 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
89 return new R600MCCodeEmitter(MCII, MRI); in createR600MCCodeEmitter()
98 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
169 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp34 const MCInstrInfo &MCII; member in __anond35bd71a0111::BPFMCCodeEmitter
41 : MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {} in BPFMCCodeEmitter()
75 MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII, in createBPFMCCodeEmitter() argument
78 return new BPFMCCodeEmitter(MCII, MRI, true); in createBPFMCCodeEmitter()
81 MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, in createBPFbeMCCodeEmitter() argument
84 return new BPFMCCodeEmitter(MCII, MRI, false); in createBPFbeMCCodeEmitter()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h39 AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in AVRMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in AVRMCCodeEmitter()
108 const MCInstrInfo &MCII; variable
H A DAVRMCELFStreamer.h26 std::unique_ptr<MCInstrInfo> MCII; variable
34 MCII(createAVRMCInstrInfo()) {} in AVRMCELFStreamer()
42 MCII(createAVRMCInstrInfo()) {} in AVRMCELFStreamer()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp43 MCInstrInfo const &MCII; member in __anone26a40d80111::RISCVMCCodeEmitter
46 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in RISCVMCCodeEmitter() argument
47 : Ctx(ctx), MCII(MCII) {} in RISCVMCCodeEmitter()
95 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, in createRISCVMCCodeEmitter() argument
98 return new RISCVMCCodeEmitter(Ctx, MCII); in createRISCVMCCodeEmitter()
196 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
272 MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); in getImmOpValue()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-ml/
H A Dllvm-ml.cpp130 MCInstrInfo &MCII, MCTargetOptions &MCOptions, in AssembleInput() argument
135 TheTarget->createMCAsmParser(STI, *Parser, MCII, MCOptions)); in AssembleInput()
316 std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); in main() local
317 assert(MCII && "Unable to create instruction info!"); in main()
325 *MCII, *MRI); in main()
341 CE.reset(TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx)); in main()
359 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); in main()
396 *MCII, MCOptions, InputArgs); in main()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mc-assemble-fuzzer/
H A Dllvm-mc-assemble-fuzzer.cpp109 MCInstrInfo &MCII, MCTargetOptions &MCOptions) { in AssembleInput() argument
116 TheTarget->createMCAsmParser(STI, *Parser, MCII, MCOptions)); in AssembleInput()
182 std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); in AssembleOneInput() local
184 *MAI, *MCII, *MRI); in AssembleOneInput()
230 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); in AssembleOneInput()
239 *MCII, MCOptions); in AssembleOneInput()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp128 std::unique_ptr<const MCInstrInfo> MCII; member in __anon0be7a23a0111::X86AsmBackend
147 MCII(T.createMCInstrInfo()) { in X86AsmBackend()
321 const MCInstrInfo &MCII) { in getCondFromBranch() argument
327 const MCInstrDesc &Desc = MCII.get(Opcode); in getCondFromBranch()
335 classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII) { in classifySecondInstInMacroFusion() argument
336 X86::CondCode CC = getCondFromBranch(MI, MCII); in classifySecondInstInMacroFusion()
341 static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII) { in isRIPRelative() argument
343 const MCInstrDesc &Desc = MCII.get(Opcode); in isRIPRelative()
355 static bool isPrefix(const MCInst &MI, const MCInstrInfo &MCII) { in isPrefix() argument
356 return X86II::isPrefix(MCII.get(MI.getOpcode()).TSFlags); in isPrefix()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h46 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
47 bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
74 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
78 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp386 std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); in main() local
387 assert(MCII && "Unable to create instruction info!"); in main()
390 TheTarget->createMCInstrAnalysis(MCII.get())); in main()
401 Triple(TripleName), IPtempOutputAsmVariant, *MAI, *MCII, *MRI)); in main()
411 mca::AsmCodeRegionGenerator CRG(*TheTarget, SrcMgr, Ctx, *MAI, *STI, *MCII); in main()
446 Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MRI)); in main()
463 mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get()); in main()
476 TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx)); in main()
538 *STI, *MCII, CE, ShowEncoding, Insts, *IP)); in main()
577 *STI, *MCII, CE, ShowEncoding, Insts, *IP)); in main()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Disassembler/
H A DWebAssemblyDisassembler.cpp43 std::unique_ptr<const MCInstrInfo> MCII; member in __anon47481f470111::WebAssemblyDisassembler
55 std::unique_ptr<const MCInstrInfo> MCII) in WebAssemblyDisassembler() argument
56 : MCDisassembler(STI, Ctx), MCII(std::move(MCII)) {} in WebAssemblyDisassembler()
63 std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo()); in createWebAssemblyDisassembler() local
64 return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII)); in createWebAssemblyDisassembler()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/
H A DVEMCCodeEmitter.cpp42 const MCInstrInfo &MCII; member in __anon36328c600111::VEMCCodeEmitter
47 : MCII(mcii), Ctx(ctx) {} in VEMCCodeEmitter()
161 MCCodeEmitter *llvm::createVEMCCodeEmitter(const MCInstrInfo &MCII, in createVEMCCodeEmitter() argument
164 return new VEMCCodeEmitter(MCII, Ctx); in createVEMCCodeEmitter()

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