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Searched refs:M0Val (Results 1 – 1 of 1) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp764 Register M0Val = MI.getOperand(6).getReg(); in selectInterpP1F16() local
765 if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI) || in selectInterpP1F16()
782 .addReg(M0Val); in selectInterpP1F16()
1277 Register M0Val = MI.getOperand(2).getReg(); in selectDSOrderedIntrinsic() local
1279 .addReg(M0Val); in selectDSOrderedIntrinsic()
1289 if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI)) in selectDSOrderedIntrinsic()