Searched refs:LogicOp (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 902 struct LogicOp { struct
903 LogicOp() = default;
904 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) in LogicOp() argument
916 static LogicOp interpretAndImmediate(unsigned Opcode) { in interpretAndImmediate()
918 case SystemZ::NILMux: return LogicOp(32, 0, 16); in interpretAndImmediate()
919 case SystemZ::NIHMux: return LogicOp(32, 16, 16); in interpretAndImmediate()
920 case SystemZ::NILL64: return LogicOp(64, 0, 16); in interpretAndImmediate()
921 case SystemZ::NILH64: return LogicOp(64, 16, 16); in interpretAndImmediate()
922 case SystemZ::NIHL64: return LogicOp(64, 32, 16); in interpretAndImmediate()
923 case SystemZ::NIHH64: return LogicOp(64, 48, 16); in interpretAndImmediate()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2734 SDValue computeLogicOpInGPR(SDValue LogicOp);
2908 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) { in computeLogicOpInGPR() argument
2909 assert(isLogicOp(LogicOp.getOpcode()) && in computeLogicOpInGPR()
2911 assert(LogicOp.getValueType() == MVT::i1 && in computeLogicOpInGPR()
2913 SDLoc dl(LogicOp); in computeLogicOpInGPR()
2917 bool IsBitwiseNegation = isBitwiseNot(LogicOp); in computeLogicOpInGPR()
2938 LHS = getLogicOperand(LogicOp.getOperand(0)); in computeLogicOpInGPR()
2939 RHS = getLogicOperand(LogicOp.getOperand(1)); in computeLogicOpInGPR()
2956 switch (LogicOp.getOpcode()) { in computeLogicOpInGPR()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 8120 Instruction *LogicOp; in splitBranchCondition() local
8123 m_Br(m_OneUse(m_Instruction(LogicOp)), TBB, FBB))) in splitBranchCondition()
8136 if (match(LogicOp, in splitBranchCondition()
8139 else if (match(LogicOp, m_LogicalOr(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
8164 LogicOp->eraseFromParent(); in splitBranchCondition()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 7944 SDValue LogicOp = Shift->getOperand(0); in combineShiftOfShiftedLogic() local
7945 if (!LogicOp.hasOneUse()) in combineShiftOfShiftedLogic()
7948 unsigned LogicOpcode = LogicOp.getOpcode(); in combineShiftOfShiftedLogic()
7987 if (matchFirstShift(LogicOp.getOperand(0), X, C0Val)) in combineShiftOfShiftedLogic()
7988 Y = LogicOp.getOperand(1); in combineShiftOfShiftedLogic()
7989 else if (matchFirstShift(LogicOp.getOperand(1), X, C0Val)) in combineShiftOfShiftedLogic()
7990 Y = LogicOp.getOperand(0); in combineShiftOfShiftedLogic()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 21919 unsigned LogicOp = IsFABS ? X86ISD::FAND : in LowerFABSorFNEG() local
21925 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
21930 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
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