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Searched refs:Load1 (Results 1 – 13 of 13) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrInfo.h420 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
438 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
H A DX86InstrInfo.cpp6548 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
6550 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
6552 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr()
6723 return Load1->getOperand(I) == Load2->getOperand(I); in areLoadsFromSameBasePtr()
6736 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp)); in areLoadsFromSameBasePtr()
6746 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
6753 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear()
6768 EVT VT = Load1->getValueType(0); in shouldScheduleLoadsNear()
H A DX86ISelLowering.cpp45461 SDValue Load1 = in combineLoad() local
45470 Load1.getValue(1), Load2.getValue(1)); in combineLoad()
45472 SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2); in combineLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h247 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
258 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
H A DARMBaseInstrInfo.cpp1924 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1930 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
1933 switch (Load1->getMachineOpcode()) { in areLoadsFromSameBasePtr()
1975 if (Load1->getOperand(0) != Load2->getOperand(0) || in areLoadsFromSameBasePtr()
1976 Load1->getOperand(4) != Load2->getOperand(4)) in areLoadsFromSameBasePtr()
1980 if (Load1->getOperand(3) != Load2->getOperand(3)) in areLoadsFromSameBasePtr()
1984 if (isa<ConstantSDNode>(Load1->getOperand(1)) && in areLoadsFromSameBasePtr()
1986 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
2005 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
2021 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && in shouldScheduleLoadsNear()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1296 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1310 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h184 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
198 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
H A DSIInstrInfo.cpp129 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr() argument
132 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode()) in areLoadsFromSameBasePtr()
136 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr()
145 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1)) in areLoadsFromSameBasePtr()
149 if (Load0->getOperand(0) != Load1->getOperand(0)) in areLoadsFromSameBasePtr()
167 Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue(); in areLoadsFromSameBasePtr()
177 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1)); in areLoadsFromSameBasePtr()
180 if (Load0->getOperand(0) != Load1->getOperand(0)) in areLoadsFromSameBasePtr()
186 dyn_cast<ConstantSDNode>(Load1->getOperand(1)); in areLoadsFromSameBasePtr()
200 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || in areLoadsFromSameBasePtr()
[all …]
H A DAMDGPURegisterBankInfo.cpp1192 auto Load1 = B.buildLoadFromOffset(Part32, PtrReg, *MMO, 8); in applyMappingLoad() local
1196 B.buildInsert(MI.getOperand(0), Ins0, Load1, 64); in applyMappingLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp1829 SDValue Load1 = DAG.getLoad(SingleTy, dl, Chain, Base1, MOp1); in SplitHvxMemOp() local
1831 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1), in SplitHvxMemOp()
1833 Load0.getValue(1), Load1.getValue(1)) }, dl); in SplitHvxMemOp()
H A DHexagonISelLowering.cpp3023 SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO); in LowerUnalignedLoad() local
3026 {Load1, Load0, BaseNoOff.getOperand(0)}); in LowerUnalignedLoad()
3028 Load0.getValue(1), Load1.getValue(1)); in LowerUnalignedLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/
H A DDataFlowSanitizer.cpp2357 Value *Load1 = in loadShadowOriginSansLoadTracking() local
2359 return {combineShadows(Load, Load1, Pos), Origin}; in loadShadowOriginSansLoadTracking()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp10231 LoadSDNode *Load1 = cast<LoadSDNode>(Op1); in tryToFoldExtendSelectLoad() local
10233 if (!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load1->getMemoryVT()) || in tryToFoldExtendSelectLoad()