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Searched refs:LastStage (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCInstrItineraries.h101 uint16_t LastStage; ///< Index of last + 1 stage in itinerary member
131 (Itineraries[ItinClassIndx].LastStage == UINT16_MAX)); in isEndMarker()
142 unsigned StageIdx = Itineraries[ItinClassIndx].LastStage; in endStage()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h190 void generateProlog(unsigned LastStage, MachineBasicBlock *KernelBB,
192 void generateEpilog(unsigned LastStage, MachineBasicBlock *KernelBB,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.h80 LastStage = ClusteredLowOccupancyReschedule enumerator
H A DGCNSchedStrategy.cpp643 } while (Stage != LastStage); in finalizeSchedule()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DModuloSchedule.cpp190 void ModuloScheduleExpander::generateProlog(unsigned LastStage, in generateProlog() argument
200 for (unsigned i = 0; i < LastStage; ++i) { in generateProlog()
248 void ModuloScheduleExpander::generateEpilog(unsigned LastStage, in generateEpilog() argument
275 int EpilogStage = LastStage + 1; in generateEpilog()
276 for (unsigned i = LastStage; i >= 1; --i, ++EpilogStage) { in generateEpilog()
289 for (unsigned StageNum = i; StageNum <= LastStage; ++StageNum) { in generateEpilog()
305 InstrMap, LastStage, EpilogStage, i == 1); in generateEpilog()
307 LastStage, EpilogStage, i == 1); in generateEpilog()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp429 int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage; in getCVIResources()
435 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources()
465 Stage < II[SchedClass].LastStage; ++Stage) { in getOtherReservedSlots()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp594 Intinerary.LastStage << ", " << in EmitItineraries()