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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZEC12.td83 def : WriteRes<LSU, [ZEC12_LSUnit]>;
88 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
122 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
123 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;
125 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCTH$")>;
126 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
127 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
132 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
146 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
154 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BRASL(_XPLINK64)?$")>;
[all …]
H A DSystemZScheduleZ196.td82 def : WriteRes<LSU, [Z196_LSUnit]>;
87 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
116 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
117 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
118 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
119 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
120 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCT(G|H)?$")>;
121 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
122 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
126 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
[all …]
H A DSystemZScheduleZ15.td88 def : WriteRes<LSU, [Z15_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
140 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
163 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
185 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
200 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
202 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
[all …]
H A DSystemZScheduleZ13.td88 def : WriteRes<LSU, [Z13_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
162 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
183 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
197 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
198 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
200 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
210 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;
[all …]
H A DSystemZScheduleZ14.td88 def : WriteRes<LSU, [Z14_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
140 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
163 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
185 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
198 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
199 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
200 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
[all …]
H A DSystemZSchedule.td22 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
29 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
43 def "LSU"#Num : SchedWrite;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp55 LSUnit::Status LSS = LSU.isAvailable(IR); in isAvailable()
87 LSU.onInstructionIssued(IR); in issueInstructionImpl()
88 const MemoryGroup &Group = LSU.getGroup(IS->getLSUTokenID()); in issueInstructionImpl()
95 LSU.onInstructionExecuted(IR); in issueInstructionImpl()
106 HasDependentUsers |= Inst.isMemOp() && LSU.hasDependentUsers(IR); in issueInstruction()
135 if (IS.isMemOp() && !LSU.isReady(IR)) { in promoteToReadySet()
172 if (IS.isMemOp() && LSU.isWaiting(IR)) { in promoteToPendingSet()
233 LSU.onInstructionExecuted(IR); in updateIssuedSet()
256 if (IS.isMemOp() && LSU.isPending(IR)) in analyzeDataDependencies()
268 LSU.cycleEvent(); in cycleEvent()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/
H A DContext.cpp41 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, in createDefaultPipeline() local
43 auto HWS = std::make_unique<Scheduler>(SM, *LSU); in createDefaultPipeline()
51 auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU); in createDefaultPipeline()
56 addHardwareUnit(std::move(LSU)); in createDefaultPipeline()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/
H A DRetireStage.h32 LSUnitBase &LSU; variable
39 : Stage(), RCU(R), PRF(F), LSU(LS) {} in RetireStage()
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/rs6000/
H A De5500.md21 ;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
36 ;; LSU.
142 ;; LSU - Loads.
153 ;; LSU - Stores.
H A De6500.md21 ;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
36 ;; LSU.
146 ;; LSU - Loads.
162 ;; LSU - Stores.
H A D6xx.md27 ;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
28 ;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
30 ;; LSU 2 stage pipelined
39 ;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
40 ;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
H A Dtitan.md92 ;; === LSU scheduling ===
109 ;; LSU, as msync is also executed within the LSU.
H A De500mc.md21 ;; e500mc 32-bit SU(2), LSU, FPU, BPU
40 ;; LSU.
/netbsd-src/external/gpl3/gcc/dist/gcc/config/rs6000/
H A De5500.md21 ;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
36 ;; LSU.
142 ;; LSU - Loads.
153 ;; LSU - Stores.
H A De6500.md21 ;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
36 ;; LSU.
146 ;; LSU - Loads.
162 ;; LSU - Stores.
H A D6xx.md27 ;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
28 ;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
30 ;; LSU 2 stage pipelined
39 ;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
40 ;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
H A Dtitan.md92 ;; === LSU scheduling ===
109 ;; LSU, as msync is also executed within the LSU.
H A De500mc64.md21 ;; e500mc64 64-bit SU(2), LSU, FPU, BPU
39 ;; LSU.
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Darm1026ejs.md47 ;; - A Load-Store Unit (LSU) pipeline.
49 ;; The LSU pipeline has decode, execute, memory, and write stages.
168 ;; LSU instructions require six cycles to execute. They use the ALU
169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
201 ;; stage in the LSU pipeline. That is modeled by keeping the ALU
H A Darm1020e.md47 ;; - A Load-Store Unit (LSU) pipeline.
49 ;; The LSU pipeline has decode, execute, memory, and write stages.
168 ;; LSU instructions require six cycles to execute. They use the ALU
169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Darm1026ejs.md47 ;; - A Load-Store Unit (LSU) pipeline.
49 ;; The LSU pipeline has decode, execute, memory, and write stages.
168 ;; LSU instructions require six cycles to execute. They use the ALU
169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
201 ;; stage in the LSU pipeline. That is modeled by keeping the ALU
H A Darm1020e.md47 ;; - A Load-Store Unit (LSU) pipeline.
49 ;; The LSU pipeline has decode, execute, memory, and write stages.
168 ;; LSU instructions require six cycles to execute. They use the ALU
169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
H A DScheduler.h71 LSUnitBase &LSU; variable
167 : LSU(Lsu), Resources(std::move(RM)), BusyResourceUnits(0), in Scheduler()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DRetireStage.cpp67 LSU.onInstructionRetired(IR); in notifyInstructionRetired()

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