Home
last modified time | relevance | path

Searched refs:LSL (Results 1 – 25 of 161) sorted by relevance

1234567

/netbsd-src/sys/arch/evbarm/lubbock/
H A Dsm_obio_space_asm.S50 add r1, r1, r2, LSL #2
53 orr r0, r0, r2, LSL #8
62 add r1, r1, r2, LSL #2
73 add r0, r1, r2, LSL #2
82 orr r1, r1, lr, LSL #8
95 add r0, r1, r2, LSL #2
122 ldrbeq r0, [r1, r2, LSL #2]
127 add r1, r1, r2, LSL #2
140 strbeq r3, [r1, r2, LSL #2]
145 mov r3, r3, LSL #8
[all …]
/netbsd-src/sys/external/bsd/gnu-efi/dist/lib/arm/
H A Ddiv.S70 subcs r0, r0, r1, LSL #7
73 subcs r0, r0, r1, LSL #6
76 subcs r0, r0, r1, LSL #5
79 subcs r0, r0, r1, LSL #4
83 subcs r0, r0, r1, LSL #3
86 subcs r0, r0, r1, LSL #2
89 subcs r0, r0, r1, LSL #1
125 subcs r0, r0, r1, LSL #7
128 subcs r0, r0, r1, LSL #6
131 subcs r0, r0, r1, LSL #5
[all …]
/netbsd-src/sys/arch/arm/xscale/
H A Dixp425_a4x_io.S55 ldr r0, [r1, r2, LSL #2]
60 ldr r0, [r1, r2, LSL #2]
67 ldr r0, [r1, r2, LSL #2]
75 str r3, [r1, r2, LSL #2]
82 str r3, [r1, r2, LSL #2]
86 str r3, [r1, r2, LSL #2]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp82 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
97 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
228 AArch64_AM::getShifterImm(AArch64_AM::LSL, in trySequenceOfOnes()
237 AArch64_AM::getShifterImm(AArch64_AM::LSL, in trySequenceOfOnes()
280 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImmSimple()
298 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImmSimple()
371 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImm()
H A DAArch64SchedPredicates.td48 def CheckShiftLSL : CheckImmOperand_s<3, "AArch64_AM::LSL">;
362 // ORR Rd, ZR, Rm, LSL #0
416 // MOVI Vd, #0, LSL #0
H A DAArch64RegisterInfo.td1130 // LSL(8|16|32|64)
1131 def ZPR#RegWidth#AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", RegWidth, 8>;
1132 def ZPR#RegWidth#AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", RegWidth, 16>;
1133 def ZPR#RegWidth#AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", RegWidth, 32>;
1134 def ZPR#RegWidth#AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", RegWidth, 64>;
1135 def ZPR#RegWidth#ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 8>;
1136 def ZPR#RegWidth#ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 16>;
1137 def ZPR#RegWidth#ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 32>;
1138 def ZPR#RegWidth#ExtLSL64 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 64>;
H A DAArch64ExpandPseudoInsts.cpp893 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in expandMI()
1088 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0), in expandMI()
1093 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0), in expandMI()
/netbsd-src/sys/arch/m68k/fpsp/
H A Dsrem_mod.sa157 LSL.L D6,D4
166 LSL.L D6,D4
168 LSL.L D6,D5
202 LSL.L D6,D1
211 LSL.L D6,D1
213 LSL.L D6,D2
301 LSL.L D6,D1
311 LSL.L D6,D1
313 LSL.L D6,D2
421 LSL.L D0,D3
H A Dslogn.sa305 LSL.L D6,D4
323 LSL.L D6,D4
325 LSL.L D6,D5
/netbsd-src/sys/arch/evbarm/smdk2xx0/
H A Dsmdk2800_start.S75 add r0,r0,r1,LSL #2
76 add r2,r2,r1,LSL #2
H A Dsmdk2410_start.S103 add r0,r0,r1,LSL #2
104 add r2,r2,r1,LSL #2
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h34 LSL = 0, enumerator
55 case AArch64_AM::LSL: return "lsl"; in getShiftExtendName()
76 case 0: return AArch64_AM::LSL; in getShiftType()
104 case AArch64_AM::LSL: STEnc = 0; break; in getShifterImm()
H A DAArch64MCCodeEmitter.cpp265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
525 assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL && in getImm8OptLsl()
/netbsd-src/sys/arch/hpc/stand/hpcboot/arm/
H A Darm_sa1100_asm.asm101 orr r6, r6, r6, LSL #8
102 orr r6, r6, r6, LSL #16
245 mov r0, r0, LSL #4
H A Darm_pxa2x0_asm.asm215 mov r0, r0, LSL #4
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1213 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
1266 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1313 ET == AArch64_AM::LSL) && in isExtend()
1332 ET == AArch64_AM::LSL) && in isExtendLSL64()
1340 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) && in isMemXExtend()
1361 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1372 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isLogicalShifter()
1383 if (ST != AArch64_AM::LSL) in isMovImm32Shifter()
1395 if (ST != AArch64_AM::LSL) in isMovImm64Shifter()
1407 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecShifter()
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dpru-opc.c102 DECLARE_FORMAT1_OPCODE (lsl, LSL),
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dpru-opc.c102 DECLARE_FORMAT1_OPCODE (lsl, LSL),
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.h38 LSL, ///< Logical shift left. enumerator
H A DAVRInstrInfo.td57 def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
1672 // 8-bit LSL is an alias of ADD Rd, Rd
1837 // LSL Rd
1841 def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8:$rd, GPR8:$rd)>;
2181 // Lowering of 'lsl' node to 'LSL' instruction.
2182 // LSL is an alias of 'ADD Rd, Rd'
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Darm1026ejs.md173 ;; those that are base + offset with LSL of 0 or 2, or base - offset
174 ;; with LSL of zero. The remainder take 1 cycle to execute.
H A Darm1020e.md173 ;; those that are base + offset with LSL of 0 or 2, or base - offset
174 ;; with LSL of zero. The remainder take 1 cycle to execute.
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Darm1026ejs.md173 ;; those that are base + offset with LSL of 0 or 2, or base - offset
174 ;; with LSL of zero. The remainder take 1 cycle to execute.
H A Darm1020e.md173 ;; those that are base + offset with LSL of 0 or 2, or base - offset
174 ;; with LSL of zero. The remainder take 1 cycle to execute.
/netbsd-src/sys/arch/evbarm/gemini/
H A Dgemini_start.S178 mov va, va, LSL #2

1234567