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Searched refs:LS1 (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp1115 LatticeCell LS1, LS2; in evaluateCMPrr() local
1116 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2)) in evaluateCMPrr()
1119 bool IsProp1 = LS1.isProperty(); in evaluateCMPrr()
1122 uint32_t Prop1 = LS1.properties(); in evaluateCMPrr()
1419 LatticeCell LS1; in evaluateANDri() local
1420 if (!getCell(R1, Inputs, LS1)) in evaluateANDri()
1422 if (LS1.isBottom() || LS1.isProperty()) in evaluateANDri()
1426 for (unsigned i = 0; i < LS1.size(); ++i) { in evaluateANDri()
1427 bool Eval = constToInt(LS1.Values[i], A) && in evaluateANDri()
1486 LatticeCell LS1; in evaluateORri() local
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/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/
H A Dthunderx3t110.md350 ; latency 4 throughput 1/2 LS0/LS1: ldr
351 ; latency 1 throughput 1 LS0/LS1,SDI,I0/I1/I2: str
606 ; tx2_ltp: x 1/2 LS0/LS1
607 ; tx3_ltp: x 1/2 LS0/LS1
609 ; tx2_ltp: x 1/2 LS0/LS1
610 ; tx3_ltp: x 1/2 LS0/LS1
613 ; tx2_ltp: x 1/2 LS0/LS1,F0/F1
614 ; tx3_ltp: x 1/2 LS0/LS1,F0/F1/F2/F3
616 ; tx2_ltp: x 1/2 LS0/LS1,F0/F1
617 ; tx3_ltp: x 1/2 LS0/LS1,F0/F1/F2/F3
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H A Dtsv110.md259 ;; 5. Two pipelines for load and store operations: LS1, LS2.
/netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/
H A Dthunderx3t110.md350 ; latency 4 throughput 1/2 LS0/LS1: ldr
351 ; latency 1 throughput 1 LS0/LS1,SDI,I0/I1/I2: str
606 ; tx2_ltp: x 1/2 LS0/LS1
607 ; tx3_ltp: x 1/2 LS0/LS1
609 ; tx2_ltp: x 1/2 LS0/LS1
610 ; tx3_ltp: x 1/2 LS0/LS1
613 ; tx2_ltp: x 1/2 LS0/LS1,F0/F1
614 ; tx3_ltp: x 1/2 LS0/LS1,F0/F1/F2/F3
616 ; tx2_ltp: x 1/2 LS0/LS1,F0/F1
617 ; tx3_ltp: x 1/2 LS0/LS1,F0/F1/F2/F3
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H A Dtsv110.md259 ;; 5. Two pipelines for load and store operations: LS1, LS2.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX3T110.td289 // 1 cycle on LS0/LS1.
295 // 2 cycles on LS0/LS1.
301 // 4 cycles on LS0/LS1.
308 // 5 cycles on LS0/LS1.
314 // 6 cycles on LS0/LS1.
320 // 4 + 5 cycles on LS0/LS1.
330 // 4 + 8 cycles on LS0/LS1.
340 // 11 cycles on LS0/LS1 and I1.
347 // 1 cycles on LS0/LS1 and I0/I1/I2/I3.
354 // 1 cycles on LS0/LS1 and 2 of I0/I1/I2/I3.
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H A DAArch64SchedThunderX2T99.td211 // 1 cycles on LS0 or LS1.
216 // 1 cycles on LS0 or LS1 and I0, I1, or I2.
222 // 1 cycles on LS0 or LS1 and 2 of I0, I1, or I2.
229 // 2 cycles on LS0 or LS1.
235 // 4 cycles on LS0 or LS1.
241 // 5 cycles on LS0 or LS1.
247 // 6 cycles on LS0 or LS1.
253 // 4 cycles on LS0 or LS1 and I0, I1, or I2.
259 // 4 cycles on LS0 or LS1 and 2 of I0, I1, or I2.
266 // 5 cycles on LS0 or LS1 and I0, I1, or I2.
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/netbsd-src/external/lgpl3/mpfr/dist/tests/
H A Dtprintf.c188 #define LS1 "%Rb %512d" in check_long_string() macro
191 err |= check_vprintf_failure (LS1, x, 1); in check_long_string()
200 err |= check_vprintf_failure (LS1 "%ln", x, 1, &n2); in check_long_string()
206 LS1 "%ln", n1, n2); in check_long_string()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/mips/
H A Dsb1.md161 ;; Indexed loads can only execute on LS1 pipe.
195 ;; Indexed stores can only execute on LS1 pipe.
221 ;; On SB-1, simple alu instructions can execute on the LS1 unit.
242 ;; insns to the LS unit, and that we don't conflict with insns that need LS1
244 ;; alu instructions that are not supposed to be scheduled to LS1 don't
245 ;; accidentally end up there because LS1 is free when they are issued. This
255 ;; On SB-1A, simple alu instructions cannot execute on the LS1 unit, and we
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/mips/
H A Dsb1.md161 ;; Indexed loads can only execute on LS1 pipe.
195 ;; Indexed stores can only execute on LS1 pipe.
221 ;; On SB-1, simple alu instructions can execute on the LS1 unit.
242 ;; insns to the LS unit, and that we don't conflict with insns that need LS1
244 ;; alu instructions that are not supposed to be scheduled to LS1 don't
245 ;; accidentally end up there because LS1 is free when they are issued. This
255 ;; On SB-1A, simple alu instructions cannot execute on the LS1 unit, and we
/netbsd-src/sys/arch/sandpoint/
H A DREADME.NAS10 tlp.11 cmdide.12 classic KuroBox, LinkStation HD-HLAN(LS1)
/netbsd-src/external/lgpl3/gmp/dist/mpn/powerpc64/
H A DREADME60 LS1 - ld/st unit 1
113 LS1 - ld/st unit 1
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Dcortex-a15.md30 ;; 5. Two pipelines for load and store operations: LS1, LS2
H A Dcortex-a57.md282 ;; 5. Two pipelines for load and store operations: LS1, LS2. The most
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Dcortex-a15.md30 ;; 5. Two pipelines for load and store operations: LS1, LS2
H A Dcortex-a57.md282 ;; 5. Two pipelines for load and store operations: LS1, LS2. The most
/netbsd-src/tests/dev/audio/
H A Daudiotest.c2700 #define LS1 (101) /* lsize + 1 */ macro
2746 } else if (len == LS1) { in test_mmap_len()
2751 } else if (offset == LS1) { in test_mmap_len()
2779 DEF(mmap_len_3) { f(LS1, 0, EOVERFLOW); } /* len is larger */ in DEF()
2782 DEF(mmap_len_6) { f(0, LS1, EINVAL); } /* len is 0 */ in DEF()
/netbsd-src/share/terminfo/
H A Dterminfo24977 # (Q) SI is also called LS1, Locking Shift One.