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Searched refs:LIS (Results 1 – 25 of 116) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSILowerControlFlow.cpp71 LiveIntervals *LIS = nullptr; member in __anonfe9ad85c0111::SILowerControlFlow
264 if (!LIS) { in emitIf()
269 LIS->InsertMachineInstrInMaps(*CopyExec); in emitIf()
273 LIS->ReplaceMachineInstrInMaps(MI, *And); in emitIf()
276 LIS->InsertMachineInstrInMaps(*Xor); in emitIf()
277 LIS->InsertMachineInstrInMaps(*SetExec); in emitIf()
278 LIS->InsertMachineInstrInMaps(*NewBr); in emitIf()
280 LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC); in emitIf()
286 LIS->removeInterval(SaveExecReg); in emitIf()
287 LIS->createAndComputeVirtRegInterval(SaveExecReg); in emitIf()
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H A DSIOptimizeExecMaskingPreRA.cpp33 LiveIntervals *LIS; member in __anonb4c9c4b40111::SIOptimizeExecMaskingPreRA
91 LiveIntervals *LIS, Register Reg, in isDefBetween() argument
93 SlotIndex AndIdx = LIS->getInstructionIndex(And); in isDefBetween()
94 SlotIndex SelIdx = LIS->getInstructionIndex(Sel); in isDefBetween()
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx); in isDefBetween()
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx)) in isDefBetween()
133 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS); in optimizeVcndVcmpPair()
149 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS); in optimizeVcndVcmpPair()
163 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS); in optimizeVcndVcmpPair()
182 if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And)) in optimizeVcndVcmpPair()
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H A DGCNRegPressure.h112 const LiveIntervals &LIS;
118 GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {} in GCNRPTracker()
198 const LiveIntervals &LIS,
202 const LiveIntervals &LIS,
212 getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) { in getLiveRegMap() argument
215 auto &SII = *LIS.getSlotIndexes(); in getLiveRegMap()
227 if (!LIS.hasInterval(Reg)) in getLiveRegMap()
229 auto &LI = LIS.getInterval(Reg); in getLiveRegMap()
250 const LiveIntervals &LIS) { in getLiveRegsAfter() argument
251 return getLiveRegs(LIS.getInstructionIndex(MI).getDeadSlot(), LIS, in getLiveRegsAfter()
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H A DSIWholeQuadMode.cpp158 LiveIntervals *LIS; member in __anon35eed8a90111::SIWholeQuadMode
320 LiveQueryResult UseLRQ = LR.Query(LIS->getInstructionIndex(UseMI)); in markDefs()
360 const MachineBasicBlock *MBB = LIS->getMBBFromIndex(Value->def); in markDefs()
368 if (const VNInfo *VN = LR.getVNInfoBefore(LIS->getMBBEndIdx(*PI))) { in markDefs()
378 MachineInstr *MI = LIS->getInstructionFromIndex(Value->def); in markDefs()
404 LiveQueryResult LRQ = LR.Query(LIS->getInstructionIndex(*MI)); in markDefs()
451 LiveRange &LR = LIS->getInterval(Reg); in markOperand()
459 LiveRange &LR = LIS->getRegUnit(*RegUnit); in markOperand()
460 const VNInfo *Value = LR.Query(LIS->getInstructionIndex(MI)).valueIn(); in markOperand()
727 LIS->InsertMachineInstrInMaps(*Save); in saveSCC()
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H A DGCNRegPressure.cpp24 const LiveIntervals &LIS, in printLivesAt() argument
27 << *LIS.getInstructionFromIndex(SI); in printLivesAt()
31 if (!LIS.hasInterval(Reg)) in printLivesAt()
33 const auto &LI = LIS.getInterval(Reg); in printLivesAt()
201 const LiveIntervals &LIS) { in getUsedRegMask() argument
214 auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex(); in getUsedRegMask()
215 return getLiveLaneMask(MO.getReg(), SI, LIS, MRI); in getUsedRegMask()
219 collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS, in collectVirtualRegUses() argument
228 auto const UsedMask = getUsedRegMask(MO, MRI, LIS); in collectVirtualRegUses()
246 const LiveIntervals &LIS, in getLiveLaneMask() argument
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H A DGCNIterativeScheduler.cpp47 const LiveIntervals *LIS, in printRegion() argument
56 if (!I->isDebugInstr() && LIS) in printRegion()
57 OS << LIS->getInstructionIndex(*I); in printRegion()
63 if (!I->isDebugInstr() && LIS) in printRegion()
64 OS << LIS->getInstructionIndex(*I); in printRegion()
69 if (LIS) OS << LIS->getInstructionIndex(*End) << '\t'; in printRegion()
78 const LiveIntervals *LIS) { in printLivenessInfo() argument
82 const auto LiveIns = getLiveRegsBefore(*Begin, *LIS); in printLivenessInfo()
87 const auto LiveOuts = getLiveRegsAfter(*BottomMI, *LIS); in printLivenessInfo()
97 printRegion(OS, R->Begin, R->End, LIS, 1); in printRegions()
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H A DSILowerSGPRSpills.cpp45 LiveIntervals *LIS = nullptr; member in __anon4b7445d60111::SILowerSGPRSpills
83 LiveIntervals *LIS) { in insertCSRSaves() argument
109 if (LIS) { in insertCSRSaves()
113 LIS->InsertMachineInstrInMaps(Inst); in insertCSRSaves()
114 LIS->removeAllRegUnitsForPhysReg(Reg); in insertCSRSaves()
123 LiveIntervals *LIS) { in insertCSRRestores() argument
146 if (LIS) { in insertCSRRestores()
148 LIS->InsertMachineInstrInMaps(Inst); in insertCSRRestores()
149 LIS->removeAllRegUnitsForPhysReg(Reg); in insertCSRRestores()
233 insertCSRSaves(*SaveBlock, CSI, LIS); in spillCalleeSavedRegs()
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H A DSIFormMemoryClauses.cpp271 LiveIntervals *LIS = &getAnalysis<LiveIntervals>(); in runOnMachineFunction() local
272 SlotIndexes *Ind = LIS->getSlotIndexes(); in runOnMachineFunction()
281 GCNDownwardRPTracker RPT(*LIS); in runOnMachineFunction()
338 SlotIndex ClauseLiveInIdx = LIS->getInstructionIndex(MI); in runOnMachineFunction()
340 LIS->getInstructionIndex(*LastClauseInst).getNextIndex(); in runOnMachineFunction()
354 const LiveInterval &LI = LIS->getInterval(R.first); in runOnMachineFunction()
409 LIS->removeInterval(Reg); in runOnMachineFunction()
410 LIS->createAndComputeVirtRegInterval(Reg); in runOnMachineFunction()
417 LIS->removeInterval(Reg); in runOnMachineFunction()
418 LIS->createAndComputeVirtRegInterval(Reg); in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp103 LiveIntervals &LIS) { in convertImplicitDefToConstZero() argument
268 const LiveIntervals &LIS) { in getVRegDef() argument
274 if (const VNInfo *ValNo = LIS.getInterval(Reg).getVNInfoBefore( in getVRegDef()
275 LIS.getInstructionIndex(*Insert))) in getVRegDef()
276 return LIS.getInstructionFromIndex(ValNo->def); in getVRegDef()
285 MachineDominatorTree &MDT, LiveIntervals &LIS) { in hasOneUse() argument
291 const LiveInterval &LI = LIS.getInterval(Reg); in hasOneUse()
293 LI.getVNInfoAt(LIS.getInstructionIndex(*Def).getRegSlot()); in hasOneUse()
296 const auto &Result = LI.Query(LIS.getInstructionIndex(*I.getParent())); in hasOneUse()
434 LiveIntervals &LIS, in oneUseDominatesOtherUses() argument
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H A DWebAssemblyMemIntrinsicResults.cpp88 LiveIntervals &LIS) { in replaceDominatedUses() argument
91 LiveInterval *FromLI = &LIS.getInterval(FromReg); in replaceDominatedUses()
92 LiveInterval *ToLI = &LIS.getInterval(ToReg); in replaceDominatedUses()
94 SlotIndex FromIdx = LIS.getInstructionIndex(MI).getRegSlot(); in replaceDominatedUses()
109 SlotIndex WhereIdx = LIS.getInstructionIndex(*Where); in replaceDominatedUses()
134 LIS.extendToIndices(*ToLI, Indices); in replaceDominatedUses()
137 LIS.shrinkToUses(FromLI); in replaceDominatedUses()
151 MachineDominatorTree &MDT, LiveIntervals &LIS, in optimizeCall() argument
174 return replaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT, LIS); in optimizeCall()
189 auto &LIS = getAnalysis<LiveIntervals>(); in runOnMachineFunction() local
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H A DWebAssemblyOptimizeLiveIntervals.cpp75 auto &LIS = getAnalysis<LiveIntervals>(); in runOnMachineFunction() local
91 LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs); in runOnMachineFunction()
112 LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg()); in runOnMachineFunction()
113 LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot()); in runOnMachineFunction()
114 LIS.RemoveMachineInstrFromMaps(*MI); in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp39 LiveInterval &LI = LIS.createEmptyInterval(VReg); in createEmptyIntervalFrom()
46 LiveInterval &OldLI = LIS.getInterval(OldReg); in createEmptyIntervalFrom()
47 VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator(); in createEmptyIntervalFrom()
66 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
86 LiveInterval &OrigLI = LIS.getInterval(Original); in scanRemattable()
90 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); in scanRemattable()
123 LiveInterval &li = LIS.getInterval(MO.getReg()); in allUsesAvailableAt()
151 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
177 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot(); in rematerializeAt()
182 LIS.removeInterval(Reg); in eraseVirtReg()
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H A DSplitKit.cpp61 : LIS(lis), LastInsertPoint(BBNum) {} in InsertPointAnalysis()
68 SlotIndex MBBEnd = LIS.getMBBEndIdx(&MBB); in computeLastInsertPoint()
87 LIP.first = LIS.getInstructionIndex(*FirstTerm); in computeLastInsertPoint()
100 LIP.second = LIS.getInstructionIndex(MI); in computeLastInsertPoint()
112 return LIS.isLiveInToMBB(CurLI, EHPad); in computeLastInsertPoint()
124 if (auto *I = LIS.getInstructionFromIndex(LIP.second)) in computeLastInsertPoint()
144 if (LIP == LIS.getMBBEndIdx(&MBB)) in getLastInsertPointIter()
146 return LIS.getInstructionFromIndex(LIP); in getLastInsertPointIter()
155 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli), in SplitAnalysis()
180 UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot()); in analyzeUses()
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H A DPHIElimination.cpp70 LiveIntervals *LIS; member in __anon58120e790111::PHIElimination
151 LIS = getAnalysisIfAvailable<LiveIntervals>(); in runOnMachineFunction()
156 if (!DisableEdgeSplitting && (LV || LIS)) { in runOnMachineFunction()
205 if (LIS) in runOnMachineFunction()
206 LIS->RemoveMachineInstrFromMaps(*DefMI); in runOnMachineFunction()
213 if (LIS) in runOnMachineFunction()
214 LIS->RemoveMachineInstrFromMaps(*I.first); in runOnMachineFunction()
379 if (LIS) { in LowerPHINode()
380 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*PHICopy); in LowerPHINode()
382 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB); in LowerPHINode()
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H A DInlineSpiller.cpp88 LiveIntervals &LIS; member in __anonf47227990111::HoistSpillHelper
142 : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()), in HoistSpillHelper()
150 IPA(LIS, mf.getNumBlockIDs()) {} in HoistSpillHelper()
161 LiveIntervals &LIS; member in __anonf47227990111::InlineSpiller
202 : MF(MF), LIS(Pass.getAnalysis<LiveIntervals>()), in InlineSpiller()
276 static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) { in getVDefInterval() argument
280 LIS.getInterval(MO.getReg()); in getVDefInterval()
297 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI)) in isSnippet()
350 LiveInterval &SnipLI = LIS.getInterval(SnipReg); in collectRegsToSpill()
387 SlotIndex Idx = LIS.getInstructionIndex(CopyMI); in hoistSpillInsideBB()
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H A DRegisterCoalescer.cpp131 LiveIntervals *LIS = nullptr; member in __anon3ec327350111::RegisterCoalescer
338 if (LIS->shrinkToUses(LI, Dead)) { in shrinkToUses()
342 LIS->splitSeparateComponents(*LI, SplitLIs); in shrinkToUses()
352 LIS->RemoveMachineInstrFromMaps(*MI); in deleteInstr()
589 LiveRangeEdit(nullptr, NewRegs, *MF, *LIS, in eliminateDeadDefs()
604 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); in adjustCopiesBackFrom()
606 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); in adjustCopiesBackFrom()
607 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot(); in adjustCopiesBackFrom()
643 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def); in adjustCopiesBackFrom()
657 LIS->getInstructionFromIndex(ValS->end.getPrevSlot()); in adjustCopiesBackFrom()
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H A DRegAllocPBQP.cpp162 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
169 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
181 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
184 void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
193 LiveIntervals &LIS = G.getMetadata().LIS; in apply() local
201 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight(); in apply()
310 LiveIntervals &LIS = G.getMetadata().LIS; in apply() local
334 LiveInterval &LI = LIS.getInterval(VReg); in apply()
529 PBQPVirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM, in PBQPVirtRegAuxInfo() argument
532 : VirtRegAuxInfo(MF, LIS, VRM, Loops, MBFI) {} in PBQPVirtRegAuxInfo()
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H A DTwoAddressInstructionPass.cpp98 LiveIntervals *LIS; member in __anond9537b180111::TwoAddressInstructionPass
200 static bool isPlainlyKilled(MachineInstr *MI, Register Reg, LiveIntervals *LIS);
290 LiveIntervals *LIS) { in isPlainlyKilled() argument
291 if (LIS && Reg.isVirtual() && !LIS->isNotInMIMap(*MI)) { in isPlainlyKilled()
298 LiveInterval &LI = LIS->getInterval(Reg); in isPlainlyKilled()
304 SlotIndex useIdx = LIS->getInstructionIndex(*MI); in isPlainlyKilled()
332 LiveIntervals *LIS, bool allowFalsePositives) { in isKilled() argument
338 if (!isPlainlyKilled(DefMI, Reg, LIS)) in isKilled()
463 if (!isPlainlyKilled(MI, RegC, LIS)) in isProfitableToCommute()
599 if (LIS) in convertInstTo3Addr()
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H A DLiveDebugVariables.cpp310 ArrayRef<unsigned> SpillOffsets, LiveIntervals &LIS,
318 LiveIntervals &LIS);
448 LiveIntervals &LIS);
464 MachineRegisterInfo &MRI, LiveIntervals &LIS);
469 LiveIntervals &LIS, LexicalScopes &LS);
474 LiveIntervals &LIS);
485 void emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
506 LiveIntervals &LIS, const TargetInstrInfo &TII,
521 void emitDebugLabel(LiveIntervals &LIS, const TargetInstrInfo &TII,
535 LiveIntervals *LIS; member in __anonfbf3834f0411::LDVImpl
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H A DRenameIndependentSubregs.cpp72 SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR, in SubRangeInfo()
74 : ConEQ(LIS), SR(&SR), Index(Index) {} in SubRangeInfo()
104 LiveIntervals *LIS; member in __anon5355d8000111::RenameIndependentSubregs
143 LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg); in INITIALIZE_PASS_DEPENDENCY()
162 SubRangeInfos.push_back(SubRangeInfo(*LIS, SR, NumComponents)); in findComponents()
189 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent()); in findComponents()
223 SlotIndex Pos = LIS->getInstructionIndex(*MI); in rewriteOperands()
271 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); in distribute()
303 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); in computeMainRangesFixFlags()
304 const SlotIndexes &Indexes = *LIS->getSlotIndexes(); in computeMainRangesFixFlags()
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H A DCalcSpillWeights.cpp41 calculateSpillWeightAndHint(LIS.getInterval(Reg)); in calculateSpillWeightsAndHints()
80 static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, in isRematerializable() argument
93 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); in isRematerializable()
113 const LiveInterval &SrcLI = LIS.getInterval(Reg); in isRematerializable()
119 MI = LIS.getInstructionFromIndex(VNI->def); in isRematerializable()
123 if (!TII.isTriviallyReMaterializable(*MI, LIS.getAliasAnalysis())) in isRematerializable()
169 const LiveInterval &OrigInt = LIS.getInterval(Original); in weightCalcHelper()
186 MachineBasicBlock *localMBB = LIS.getMBBFromIndex(*End); in weightCalcHelper()
187 assert(localMBB == LIS.getMBBFromIndex(*Start) && in weightCalcHelper()
226 SlotIndex SI = LIS.getInstructionIndex(*MI); in weightCalcHelper()
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H A DRegAllocBase.cpp62 LIS = &lis; in init()
78 enqueue(&LIS->getInterval(Reg)); in seedLiveRegs()
95 LIS->removeInterval(VirtReg->reg()); in allocatePhysRegs()
150 assert(LIS->hasInterval(Reg)); in allocatePhysRegs()
152 LiveInterval *SplitVirtReg = &LIS->getInterval(Reg); in allocatePhysRegs()
158 LIS->removeInterval(SplitVirtReg->reg()); in allocatePhysRegs()
173 LIS->RemoveMachineInstrFromMaps(*DeadInst); in postOptimization()
H A DRegisterPressure.cpp237 static const LiveRange *getLiveRange(const LiveIntervals &LIS, unsigned Reg) { in getLiveRange() argument
239 return &LIS.getInterval(Reg); in getLiveRange()
240 return LIS.getCachedRegUnit(Reg); in getLiveRange()
245 LIS = nullptr; in reset()
281 LIS = lis; in init()
314 return LIS->getMBBEndIdx(MBB); in getCurrSlot()
315 return LIS->getInstructionIndex(*IdxPos).getRegSlot(); in getCurrSlot()
422 getLanesWithProperty(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, in getLanesWithProperty() argument
427 const LiveInterval &LI = LIS.getInterval(RegUnit); in getLanesWithProperty()
441 const LiveRange *LR = LIS.getCachedRegUnit(RegUnit); in getLanesWithProperty()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp67 LiveIntervals *LIS; member
109 SlotIndex FMAIdx = LIS->getInstructionIndex(MI); in processBlock()
112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
118 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def); in processBlock()
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
213 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) in processBlock()
281 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg); in processBlock()
299 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg); in processBlock()
308 LIS->getVNInfoAllocator()); in processBlock()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp169 LiveIntervals *LIS = nullptr; member in __anon198387370111::HexagonExpandCondsets
319 MachineInstr *MI = LIS->getInstructionFromIndex(K); in updateKillFlags()
335 LiveInterval &LI = LIS->getInterval(Reg); in updateKillFlags()
343 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start); in updateKillFlags()
420 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); in updateDeadsInRange()
427 LiveInterval &LI = LIS->getInterval(Reg); in updateDeadsInRange()
428 LI.computeSubRangeUndefs(Undefs, LM, *MRI, *LIS->getSlotIndexes()); in updateDeadsInRange()
431 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI); in updateDeadsInRange()
432 auto P = Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI); in updateDeadsInRange()
443 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI); in updateDeadsInRange()
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