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Searched refs:LDR (Results 1 – 25 of 87) sorted by relevance

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/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/arm/
H A Dfreebsd-atomic.c59 #define SYNC_LOCK_TEST_AND_SET_N(N, TYPE, LDR, STR) \ argument
74 "\t"LDR" %0, %4\n" /* Load old value. */ \
98 #define SYNC_VAL_CAS_N(N, TYPE, LDR, STREQ) \ argument
114 "\t"LDR" %0, %5\n" /* Load old value. */ \
142 #define SYNC_FETCH_AND_OP_N(N, TYPE, LDR, STR, NAME, OP) \ argument
157 "\t"LDR" %0, %4\n" /* Load old value. */ \
172 #define SYNC_OP_AND_FETCH_N(N, TYPE, LDR, STR, NAME, OP) \ argument
187 "\t"LDR" %0, %5\n" /* Load old value. */ \
202 #define EMIT_ALL_OPS_N(N, TYPE, LDR, STR, STREQ) \ argument
203 SYNC_LOCK_TEST_AND_SET_N (N, TYPE, LDR, STR) \
[all …]
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/arm/
H A Dfreebsd-atomic.c59 #define SYNC_LOCK_TEST_AND_SET_N(N, TYPE, LDR, STR) \ argument
74 "\t"LDR" %0, %4\n" /* Load old value. */ \
98 #define SYNC_VAL_CAS_N(N, TYPE, LDR, STREQ) \ argument
114 "\t"LDR" %0, %5\n" /* Load old value. */ \
142 #define SYNC_FETCH_AND_OP_N(N, TYPE, LDR, STR, NAME, OP) \ argument
157 "\t"LDR" %0, %4\n" /* Load old value. */ \
172 #define SYNC_OP_AND_FETCH_N(N, TYPE, LDR, STR, NAME, OP) \ argument
187 "\t"LDR" %0, %5\n" /* Load old value. */ \
202 #define EMIT_ALL_OPS_N(N, TYPE, LDR, STR, STREQ) \ argument
203 SYNC_LOCK_TEST_AND_SET_N (N, TYPE, LDR, STR) \
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/netbsd-src/sys/external/bsd/compiler_rt/dist/lib/xray/
H A Dxray_trampoline_AArch64.S30 LDR X1, =_ZN6__xray19XRayPatchedFunctionE
32 LDR X2, [X1]
74 LDR X1, =_ZN6__xray19XRayPatchedFunctionE
76 LDR X2, [X1]
86 LDR Q0, [SP], #16
118 LDR X1, =_ZN6__xray19XRayPatchedFunctionE
120 LDR X2, [X1]
H A Dxray_trampoline_arm.S25 LDR r2, [r1]
56 LDR r2, [r1]
86 LDR r2, [r1]
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DBigEndianNEON.rst52 ``LDR`` and ``LD1``
58 Big endian vector load using ``LDR``.
61 …In little endian mode, we can do this by just performing a 64-bit load - ``LDR q0, [foo]``. Howeve…
75 …1. The content of a vector register is the same *as if* it had been loaded with an ``LDR`` instruc…
78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si…
95 Use of ``LDR`` would break this lane ordering property. This doesn't preclude the use of ``LDR``, b…
97 1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``.
105 …e register; a short vector is loaded from memory using the corresponding ``LDR`` instruction. On a…
109 The use of ``LDR`` and ``STR`` as the ABI defines has at least one advantage over ``LD1`` and ``ST1…
128 So to preserve ABI compatibility, we need to use the ``LDR`` lane layout across function calls.
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Dfa626te.md25 ;; ALU -> simple address LDR/STR: latency = 2 (available after 2 cycles).
26 ;; ALU -> shifted address LDR/STR: latency = 3.
29 ;; LD -> simple address LDR/STR: latency = 3 (available after 3 cycles).
30 ;; LD -> shifted address LDR/STR: latency = 4
H A Dcortex-m4.md23 ;; We model the pipelining of LDR instructions by using two artificial units.
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Dfa626te.md25 ;; ALU -> simple address LDR/STR: latency = 2 (available after 2 cycles).
26 ;; ALU -> shifted address LDR/STR: latency = 3.
29 ;; LD -> simple address LDR/STR: latency = 3 (available after 3 cycles).
30 ;; LD -> shifted address LDR/STR: latency = 4
H A Dcortex-m4.md23 ;; We model the pipelining of LDR instructions by using two artificial units.
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/arm/
H A Dmisaligned2.ms1 # Test LDR instructions with offsets misaligned by 2 bytes.
H A Dmisaligned1.ms1 # Test LDR instructions with offsets misaligned by 1 byte.
H A Dmisaligned3.ms1 # Test LDR instructions with offsets misaligned by 3 bytes.
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/mips/
H A Dr6-removed.csv17 LDR,0x6c000000
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td412 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(W|X)l$")>;
415 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(BB|HH|W|X)ui$")>;
418 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr], (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
497 def : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[DSQ]l")>;
499 def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
500 def : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[BDHSQ]ui")>;
501 def : InstRW<[TSV110Wr_6cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
H A DAArch64SchedExynosM3.td518 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
520 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
562 def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>;
565 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
566 def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>;
568 ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
570 ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
H A DAArch64SchedExynosM5.td672 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
674 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
733 def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>;
736 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>;
737 def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>;
739 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
741 ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
H A DAArch64SchedExynosM4.td615 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
617 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
677 def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>;
680 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>;
681 def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>;
683 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
685 ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
H A DAArch64SchedFalkorDetails.td1092 (instregex "^LDR((Q|D|S|H|B)ui|(Q|D|S)l)$")>;
1094 (instregex "^LDR(Q|D|S|H|B)(post|pre)$")>;
1098 (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
1174 (instregex "^LDR(BB|HH|W|X)ui$")>;
1176 (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
1178 (instregex "^LDR(BB|HH|W|X)ro(W|X)$")>;
1180 (instregex "^LDR(W|X)l$")>;
/netbsd-src/distrib/acorn32/stand/BtNetBSD/!BtNetBSD/
H A DBtNetBSD885 LDR r2, [r0], #4
940 LDR r6, [r5], #4 ; r4 = number of relocated pages
942 LDR r2, [r5], #4 ; r2 = from address
943 LDR r3, [r5], #4 ; r3 = to address
944 LDR r7, [r5], #4 ; r7 = number of bytes to travel
997 LDR r0, [r5], #4
1211 LDR r4, [r3, #8]
1212 LDR r5, [r3, #20]
/netbsd-src/sys/arch/arm/arm/
H A Dcpufunc_asm_pj4b.S80 bic r0, r0, #(1 << 23) @ Enable fast LDR
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DREADME.txt504 Split out LDR (literal) from normal ARM LDR instruction. Also consider spliting
505 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
506 ARMLoadStoreOptimizer does not need to look at LDR (literal) and LDR (so_reg)
507 while ARMConstantIslandPass only need to worry about LDR (literal).
H A DARMScheduleA57.td378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate
391 def : InstRW<[A57WriteLdrAm3], (instregex "LDR(H|SH|SB)$")>;
419 // --- LDR pre-indexed ---
438 (instregex "LDR(H|SH|SB)_PRE")>;
456 // --- LDR post-indexed ---
457 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackOne], (instregex "LDR(T?)_POST_IMM",
458 "LDRB(T?)_POST_IMM", "LDR(SB|H|SH)Ti", "t2LDRB_POST")>;
465 (instregex "LDR(H|SH|SB)_POST")>;
470 "LDRB_POST_REG", "LDR(B?)T_POST$")>;
484 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR(SB|H|SH)Tr")>;
H A DARMScheduleSwift.td357 (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
367 "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
370 (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
540 // LDRLIT pseudo instructions, they expand to LDR + PICADD
543 // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
/netbsd-src/external/gpl3/binutils/dist/gas/doc/
H A Dc-aarch64.texi366 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
367 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
586 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
587 @item LDR =
593 already there) and a PC-relative LDR instruction will be generated.
/netbsd-src/external/gpl3/binutils.old/dist/gas/doc/
H A Dc-aarch64.texi309 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
310 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
534 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
535 @item LDR =
541 already there) and a PC-relative LDR instruction will be generated.

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