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Searched refs:LDM (Results 1 – 25 of 73) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DAddDiscriminators.cpp184 LocationDiscriminatorMap LDM; in addDiscriminators() local
211 unsigned Discriminator = R.second ? ++LDM[L] : LDM[L]; in addDiscriminators()
248 unsigned Discriminator = ++LDM[L]; in addDiscriminators()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/bpf/
H A Dbpf.md486 (define_mode_iterator LDM [QI HI SI DI])
490 [(set (reg:LDM R0_REGNUM)
491 (unspec:LDM [(match_operand:DI 0 "register_operand" "r")
503 [(set (reg:LDM R0_REGNUM)
504 (unspec:LDM [(match_operand:SI 0 "imm32_operand" "I")
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/bpf/
H A Dbpf.md480 (define_mode_iterator LDM [QI HI SI DI])
484 [(set (reg:LDM R0_REGNUM)
485 (unspec:LDM [(match_operand:DI 0 "register_operand" "r")
497 [(set (reg:LDM R0_REGNUM)
498 (unspec:LDM [(match_operand:SI 0 "imm32_operand" "I")
/netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/sha/asm/
H A Dsha512-parisc.pl69 $LDM="ldd,ma";
81 $LDM="ldwm";
133 `"$LDM $SZ($Tbl),$t1" if ($i<15)`
155 $LDM $SZ($Tbl),$t1
298 $LDM $SZ($Tbl),$t1
/netbsd-src/crypto/external/bsd/openssl/dist/crypto/sha/asm/
H A Dsha512-parisc.pl72 $LDM="ldd,ma";
84 $LDM="ldwm";
136 `"$LDM $SZ($Tbl),$t1" if ($i<15)`
158 $LDM $SZ($Tbl),$t1
301 $LDM $SZ($Tbl),$t1
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleM4.td55 def : M4UnitL2I<(instregex "(t|t2)LDM")>;
H A DARMScheduleSwift.td482 (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
483 "(t|sys)LDM(IA|DA|DB|IB)$")>;
486 "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
H A DARMScheduleR52.td480 (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
481 "(t|sys)LDM(IA|DA|DB|IB)$")>;
483 (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
H A DARMScheduleM7.td243 (instregex "(t|t2)LDM(DB|IA)$")>;
247 (instregex "(t|t2)LDM(DB|IA)_UPD$", "tPOP")>;
H A DARMScheduleA9.td2049 // Define a predicate to select the LDM based on number of memory addresses.
2058 // LDM/VLDM/VLDn address generation latency & resources.
2069 // For unknown LDM/VLDM/VSTM, assume 2 32-bit registers.
2072 // Define LDM Resources.
2092 // LDM: Load multiple into 32-bit integer registers.
2247 // tuple, unlike LDM. So the number of write operands is not variadic.
2253 // Resources for other (non-LDM/VLDM) Variants.
H A DARMSchedule.td189 // LDM, base reg in list
H A DARMBaseInstrInfo.cpp1607 MachineInstrBuilder LDM, STM; in expandMEMCPY() local
1610 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD in expandMEMCPY()
1615 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA)); in expandMEMCPY()
1629 LDM.add(LDBase).add(predOps(ARMCC::AL)); in expandMEMCPY()
1646 LDM.addReg(Reg, RegState::Define); in expandMEMCPY()
H A DARMScheduleA57.td590 def : InstRW<[A57WriteLDM], (instregex "(t|t2|sys)?LDM(IA|DA|DB|IB)$")>;
594 (instregex "(t|t2|sys)?LDM(IA_UPD|DA_UPD|DB_UPD|IB_UPD|IA_RET)", "tPOP")>;
H A DARMInstrThumb.td1645 // post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Darm1020e.md190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
201 ;; a register dependency; the dependency is cleared as soon as the LDM/STM
H A Dfa726te.md160 ;; The LDM is breaking into multiple load instructions, later instruction in
H A Darm1026ejs.md190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
H A Dcortex-a53.md169 ;; Model AArch32-sized LDM Ra, {Rm, Rn, Ro}
H A Dconstraints.md532 ; are actually LDM/STM instructions, so cannot be used to access unaligned
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Darm1020e.md190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
201 ;; a register dependency; the dependency is cleared as soon as the LDM/STM
H A Dfa726te.md160 ;; The LDM is breaking into multiple load instructions, later instruction in
H A Darm1026ejs.md190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
H A Dcortex-a53.md169 ;; Model AArch32-sized LDM Ra, {Rm, Rn, Ro}
H A Dconstraints.md547 ; are actually LDM/STM instructions, so cannot be used to access unaligned
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td249 // TODO: LDM and STM.

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