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Searched refs:LAR (Results 1 – 14 of 14) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DLoopPassManager.cpp204 LoopStandardAnalysisResults LAR = {AM.getResult<AAManager>(F), in run() local
241 PI.pushBeforeNonSkippedPassCallback([&LAR, &LI](StringRef PassID, Any IR) { in run()
252 assert(L->isRecursivelyLCSSAForm(LAR.DT, LI) && in run()
279 PassPA = Pass->run(*L, LAM, LAR, Updater); in run()
293 LAR.DT.verify(); in run()
295 LAR.LI.verify(LAR.DT); in run()
296 if (LAR.MSSA && VerifyMemorySSA) in run()
297 LAR.MSSA->verifyMemorySSA(); in run()
H A DLoopVersioningLICM.cpp667 LoopStandardAnalysisResults &LAR, in run() argument
669 AliasAnalysis *AA = &LAR.AA; in run()
670 ScalarEvolution *SE = &LAR.SE; in run()
671 DominatorTree *DT = &LAR.DT; in run()
672 LoopInfo *LI = &LAR.LI; in run()
677 return AM.getResult<LoopAccessAnalysis>(*L, LAR); in run()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Scalar/
H A DLoopVersioningLICM.h20 LoopStandardAnalysisResults &LAR, LPMUpdater &U);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
H A DLoopVectorizationLegality.cpp865 const OptimizationRemarkAnalysis *LAR = LAI->getReport(); in canVectorizeMemory() local
866 if (LAR) { in canVectorizeMemory()
869 "loop not vectorized: ", *LAR); in canVectorizeMemory()
/netbsd-src/tests/fs/cd9660/
H A Dpr_48787.image.hex136 0001a150 06 0f 1e 12 00 00 00 00 01 00 00 01 0d 4c 41 52 |.............LAR|
258 1020fa150 06 0f 1e 12 00 00 00 00 01 00 00 01 0d 4c 41 52 |.............LAR|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DScalarEvolution.cpp10519 const auto *LAR = cast<SCEVAddRecExpr>(Less); in computeConstantDifference() local
10522 if (LAR->getLoop() != MAR->getLoop()) in computeConstantDifference()
10527 if (!LAR->isAffine() || !MAR->isAffine()) in computeConstantDifference()
10530 if (LAR->getStepRecurrence(*this) != MAR->getStepRecurrence(*this)) in computeConstantDifference()
10533 Less = LAR->getStart(); in computeConstantDifference()
10844 const SCEVAddRecExpr *LAR = dyn_cast<SCEVAddRecExpr>(LHS); in IsKnownPredicateViaAddRecStart() local
10845 if (!LAR) in IsKnownPredicateViaAddRecStart()
10850 if (LAR->getLoop() != RAR->getLoop()) in IsKnownPredicateViaAddRecStart()
10852 if (!LAR->isAffine() || !RAR->isAffine()) in IsKnownPredicateViaAddRecStart()
10855 if (LAR->getStepRecurrence(SE) != RAR->getStepRecurrence(SE)) in IsKnownPredicateViaAddRecStart()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86SchedBroadwell.td1254 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1349 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
H A DX86SchedSkylakeClient.td905 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1312 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
H A DX86SchedHaswell.td1437 def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
1444 def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
H A DX86SchedSkylakeServer.td1025 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1755 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
H A DX86ScheduleBdVer2.td313 def : InstRW<[PdWriteLARrr], (instregex "LAR(16|32|64)rr",
/netbsd-src/share/misc/
H A Dacronyms.comp894 LAR load access rights
H A Dairport4095 LAR:Laramie Regional Airport, WY, USA
/netbsd-src/external/gpl3/binutils/dist/
H A DChangeLog.git37715 (where S is used, matching LAR/LSL), to also behave correctly in suffix-
37722 x86: simplify disassembly of LAR/LSL
37723 For whatever reason in c9f5b96bdab0 ("x86: correct handling of LAR and
67897 x86-64: LAR and LSL don't need REX.W
67899 register, there's also no need for it for LAR and LSL - these can only
84436 x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR and LSL"
84438 register source for LAR and LSL"), adjusting testcases as necessary.
84440 handling of LAR and LSL"), without actually saying so. While the earlier
85650 x86: Allow 16-bit register source for LAR and LSL
85651 Since LAR and LSL only access 16 bits of the source operand, regardless
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