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Searched refs:IssueWidth (Results 1 – 25 of 77) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp74 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
106 if (IssueWidth == 0) in atIssueLimit()
109 return IssueCount == IssueWidth; in atIssueLimit()
H A DTargetSchedule.cpp71 ResourceLCM = SchedModel.IssueWidth; in init()
77 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCSchedule.cpp106 return ((double)SCDesc.NumMicroOps) / SM.IssueWidth; in getReciprocalThroughput()
119 return 1.0 / IssueWidth; in getReciprocalThroughput()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp226 unsigned IssueWidth = TSM.getIssueWidth(); in addPadding() local
228 for (unsigned i = 0, e = IssueWidth * NOOPsToAdd; i != e; ++i) in addPadding()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp43 bool ShouldCarryOver = NumMicroOps > SM.IssueWidth; in isAvailable()
346 Bandwidth = SM.IssueWidth; in cycleStart()
367 assert(NumIssued <= SM.IssueWidth && "Overflow."); in cycleStart()
H A DDispatchStage.cpp35 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DScoreboardHazardRecognizer.h99 unsigned IssueWidth = 0; variable
H A DTargetSchedule.h99 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV62.td28 let IssueWidth = 4;
H A DHexagonScheduleV68.td30 let IssueWidth = 4;
H A DHexagonScheduleV55.td39 let IssueWidth = 4;
H A DHexagonScheduleV66.td31 let IssueWidth = 4;
H A DHexagonScheduleV65.td31 let IssueWidth = 4;
H A DHexagonScheduleV5.td37 let IssueWidth = 4;
H A DHexagonScheduleV67.td31 let IssueWidth = 4;
H A DHexagonScheduleV67T.td53 let IssueWidth = 3;
H A DHexagonScheduleV60.td72 let IssueWidth = 4;
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
H A DSummaryView.cpp27 : SM(Model), Source(S), DispatchWidth(Width?Width: Model.IssueWidth), in SummaryView()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td39 let IssueWidth = 1;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCSchedule.h257 unsigned IssueWidth; member
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCScheduleA2.td159 let IssueWidth = 1; // 1 instruction is dispatched per cycle.
H A DPPCScheduleG5.td118 let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td19 let IssueWidth = 8; // 8 uops are dispatched per cycle.
H A DAArch64SchedKryo.td20 let IssueWidth = 5; // 5-wide issue for expanded uops
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleM4.td14 let IssueWidth = 1; // Only IT can be dual-issued, so assume single-issue

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