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Searched refs:IsVecInReg (Results 1 – 1 of 1) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1885 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in SimplifyDemandedBits() local
1891 if (IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
1897 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; in SimplifyDemandedBits()
1923 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; in SimplifyDemandedBits() local
1929 if (IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
1935 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; in SimplifyDemandedBits()
1959 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; in SimplifyDemandedBits()
1976 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG; in SimplifyDemandedBits() local
1980 if (IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()