Home
last modified time | relevance | path

Searched refs:IsUndef (Results 1 – 19 of 19) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineOperand.h132 unsigned IsUndef : 1; variable
397 return IsUndef; in isUndef()
513 IsUndef = Val;
805 Op.IsUndef = isUndef;
H A DMachineInstr.h1590 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp244 bool IsUndef = true; in shrinkMIMG() local
256 IsUndef = false; in shrinkMIMG()
291 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef); in shrinkMIMG()
366 const bool IsUndef = SrcReg->isUndef(); in shrinkScalarLogicOp() local
375 /*isDead*/ false, IsUndef); in shrinkScalarLogicOp()
H A DGCNHazardRecognizer.cpp898 bool IsUndef = Src0->isUndef(); in fixVcmpxPermlaneHazards() local
901 .addReg(Reg, RegState::Define | (IsUndef ? RegState::Dead : 0)) in fixVcmpxPermlaneHazards()
902 .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill); in fixVcmpxPermlaneHazards()
H A DSIInstrInfo.cpp1815 bool IsUndef = MI.getOperand(1).isUndef(); in expandPostRAPseudo() local
1824 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)); in expandPostRAPseudo()
1843 bool IsUndef = MI.getOperand(1).isUndef(); in expandPostRAPseudo() local
1859 RegState::Implicit | (IsUndef ? RegState::Undef : 0)); in expandPostRAPseudo()
1883 bool IsUndef = MI.getOperand(1).isUndef(); in expandPostRAPseudo() local
1895 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)) in expandPostRAPseudo()
2047 bool IsUndef = RegOp.isUndef(); in swapRegAndNonRegOperand() local
2063 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug); in swapRegAndNonRegOperand()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h185 bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
189 void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
/netbsd-src/external/apache2/llvm/dist/clang/include/clang/Basic/
H A DTargetBuiltins.h264 bool isUndef() const { return Flags & IsUndef; } in isUndef()
H A Darm_sve.td204 def IsUndef : FlagType<0x80000000>; // Codegen `undef` of given type.
1438 def SVUNDEF_1 : SInst<"svundef_{d}", "d", "csilUcUsUiUlhfd", MergeNone, "", [IsUndef]>;
1439 def SVUNDEF_2 : SInst<"svundef2_{d}", "2", "csilUcUsUiUlhfd", MergeNone, "", [IsUndef]>;
1440 def SVUNDEF_3 : SInst<"svundef3_{d}", "3", "csilUcUsUiUlhfd", MergeNone, "", [IsUndef]>;
1441 def SVUNDEF_4 : SInst<"svundef4_{d}", "4", "csilUcUsUiUlhfd", MergeNone, "", [IsUndef]>;
1448 def SVUNDEF_1_BF16 : SInst<"svundef_{d}", "d", "b", MergeNone, "", [IsUndef]>;
1449 def SVUNDEF_2_BF16 : SInst<"svundef2_{d}", "2", "b", MergeNone, "", [IsUndef]>;
1450 def SVUNDEF_3_BF16 : SInst<"svundef3_{d}", "3", "b", MergeNone, "", [IsUndef]>;
1451 def SVUNDEF_4_BF16 : SInst<"svundef4_{d}", "4", "b", MergeNone, "", [IsUndef]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp166 bool IsUndef = false; in tryCombineConcatVectors() local
168 if (matchCombineConcatVectors(MI, IsUndef, Ops)) { in tryCombineConcatVectors()
169 applyCombineConcatVectors(MI, IsUndef, Ops); in tryCombineConcatVectors()
175 bool CombinerHelper::matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef, in matchCombineConcatVectors() argument
179 IsUndef = true; in matchCombineConcatVectors()
191 IsUndef = false; in matchCombineConcatVectors()
221 MachineInstr &MI, bool IsUndef, const ArrayRef<Register> Ops) { in applyCombineConcatVectors() argument
234 if (IsUndef) in applyCombineConcatVectors()
H A DLegalizerHelper.cpp5142 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF; in narrowScalarCTLZ() local
5150 auto LoCTLZ = IsUndef ? in narrowScalarCTLZ()
5178 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF; in narrowScalarCTTZ() local
5186 auto HiCTTZ = IsUndef ? in narrowScalarCTTZ()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineInstr.cpp2018 void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) { in setRegisterDefReadUndef() argument
2022 MO.setIsUndef(IsUndef); in setRegisterDefReadUndef()
H A DRegisterCoalescer.cpp1697 bool IsUndef = true; in addUndefFlag() local
1702 IsUndef = false; in addUndefFlag()
1706 if (IsUndef) { in addUndefFlag()
H A DMachineOperand.cpp263 IsUndef = isUndef; in ChangeToRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp512 bool IsSplat = true, IsUndef = true; in buildHvxVectorReg() local
517 IsUndef = false; in buildHvxVectorReg()
523 if (IsUndef) in buildHvxVectorReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DInstructionSimplify.cpp4807 bool IsUndef = Q.isUndefValue(V); in simplifyFPOp() local
4812 if (FMF.noNaNs() && (IsNan || IsUndef)) in simplifyFPOp()
4814 if (FMF.noInfs() && (IsInf || IsUndef)) in simplifyFPOp()
4817 if (IsUndef || IsNan) in simplifyFPOp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3736 bool IsUndef = true; in loadRegPairFromStackSlot() local
3742 IsUndef = false; in loadRegPairFromStackSlot()
3745 .addReg(DestReg0, RegState::Define | getUndefRegState(IsUndef), SubIdx0) in loadRegPairFromStackSlot()
3746 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/netbsd-src/external/apache2/llvm/dist/clang/lib/Serialization/
H A DASTReader.cpp594 bool IsUndef = PPOpts.Macros[I].second; in collectMacroDefinitions() local
601 if (IsUndef) { in collectMacroDefinitions()
5880 bool IsUndef = Record[Idx++]; in ParsePreprocessorOptions() local
5881 PPOpts.Macros.push_back(std::make_pair(Macro, IsUndef)); in ParsePreprocessorOptions()
/netbsd-src/external/apache2/llvm/dist/llvm/bindings/go/llvm/
H A Dir.go810 func (v Value) IsUndef() bool { return C.LLVMIsUndef(v.C) != 0 } func
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp5804 bool IsUndef = Values[i] < 0 && IsMask; in getConstVector() local
5805 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) : in getConstVector()
5809 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) : in getConstVector()