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Searched refs:IsStore (Results 1 – 24 of 24) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp158 bool IsStore = false; in emitInstruction() local
160 &IsStore); in emitInstruction()
166 bool MaskAfter = IsSPFirstOperand && !IsStore; in emitInstruction()
211 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
212 if (IsStore) in isBasePlusOffsetMemoryAccess()
213 *IsStore = false; in isBasePlusOffsetMemoryAccess()
243 if (IsStore) in isBasePlusOffsetMemoryAccess()
244 *IsStore = true; in isBasePlusOffsetMemoryAccess()
251 if (IsStore) in isBasePlusOffsetMemoryAccess()
252 *IsStore = true; in isBasePlusOffsetMemoryAccess()
H A DMipsMCNaCl.h21 bool *IsStore = nullptr);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp395 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
402 if (IsStore && MI->mayLoad()) in canHoistLoadStoreTo()
423 bool IsStore = Ldst->mayStore(); in canSinkLoadStoreTo() local
433 if (IsStore && MI->mayLoad()) in canSinkLoadStoreTo()
444 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
454 if (IsStore) { in changeToAddrMode()
461 if (IsStore) in changeToAddrMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp75 unsigned int IsStore : 1; member
367 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
373 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
681 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
698 !SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
703 if (SwapVector[UseOfUseIdx].IsStore) { in recordUnoptimizableWebs()
720 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
728 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
794 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
1006 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kCollapseMOVEMPass.cpp204 bool IsStore = false) { in ProcessMI() argument
209 if (State.isStore() == IsStore && State.getBase() == Reg && in ProcessMI()
218 return ProcessMI(MBB, MI, State, Mask, Offset, Reg, IsStore); in ProcessMI()
227 IsStore ? State.setStore() : State.setLoad(); in ProcessMI()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td36 bit IsStore = false;
52 let TSFlags{6...6} = IsStore;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td794 bit IsStore = ?;
1098 let IsStore = true;
1103 let IsStore = true;
1110 let IsStore = true;
1115 let IsStore = true;
1121 let IsStore = true;
1127 let IsStore = true;
1133 let IsStore = true;
1138 let IsStore = true;
1143 let IsStore = true;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp931 bool IsStore = MI->mayStore(); in spillVGPRtoAGPR() local
935 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
936 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
937 unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 in spillVGPRtoAGPR()
956 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
959 int LoadStoreOp = IsStore ? in buildMUBUFOffsetLoadStore()
989 bool IsStore = TII->get(LoadStoreOp).mayStore(); in getFlatScratchSpillOpcode() local
996 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in getFlatScratchSpillOpcode()
1000 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR in getFlatScratchSpillOpcode()
1004 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR in getFlatScratchSpillOpcode()
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H A DAMDGPUInstructions.td365 let IsStore = 1;
443 let IsStore = 1;
450 let IsStore = 1;
460 let IsStore = 1;
466 let IsStore = 1;
525 let IsStore = 1;
531 let IsStore = 1;
H A DSIInstrInfo.td448 let IsStore = 1;
454 let IsStore = 1;
460 let IsStore = 1;
466 let IsStore = 1;
472 let IsStore = 1;
476 let IsStore = 1, AddressSpaces = StoreAddress_local.AddrSpaces in {
479 let IsStore = 1;
485 let IsStore = 1;
491 let IsStore = 1;
499 let IsStore = 1;
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H A DAMDGPULegalizerInfo.cpp1082 const bool IsStore = Op == G_STORE; in AMDGPULegalizerInfo() local
1137 if (!IsStore) { in AMDGPULegalizerInfo()
1255 if (IsStore) in AMDGPULegalizerInfo()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DX86FoldTablesEmitter.cpp104 bool IsStore = false; member in __anonf4dbc8260111::X86FoldTablesEmitter::X86FoldTableEntry
121 if (IsStore) in print()
479 Result.IsStore = true; in addEntryWithFlags()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp466 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
485 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
H A DARMLoadStoreOptimizer.cpp500 bool IsStore = in UpdateBaseRegUses() local
503 if (IsLoad || IsStore) { in UpdateBaseRegUses()
516 if (Offset >= 0 && !(IsStore && InstrSrcReg == Base)) in UpdateBaseRegUses()
/netbsd-src/external/apache2/llvm/dist/clang/include/clang/Basic/
H A Darm_sve.td186 def IsStore : FlagType<0x00004000>;
549 def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch6…
550 def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore], MemEltTyInt8, "aarch6…
551 def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore], MemEltTyInt8, "aarch6…
552 def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore], MemEltTyInt16, "aarch6…
553 def SVST1H_U : MInst<"svst1h[_{d}]", "vPFd", "UiUl", [IsStore], MemEltTyInt16, "aarch6…
554 def SVST1W_S : MInst<"svst1w[_{d}]", "vPCd", "l", [IsStore], MemEltTyInt32, "aarch6…
555 def SVST1W_U : MInst<"svst1w[_{d}]", "vPGd", "Ul", [IsStore], MemEltTyInt32, "aarch6…
558 def SVST1_VNUM : MInst<"svst1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefau…
559 def SVST1B_VNUM_S : MInst<"svst1b_vnum[_{d}]", "vPAld", "sil", [IsStore], MemEltTyInt8,…
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H A DTargetBuiltins.h246 bool isStore() const { return Flags & IsStore; } in isStore()
/netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/
H A DCGAtomic.cpp1288 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
1309 if (IsStore) in EmitAtomicExpr()
1321 if (IsLoad || IsStore) in EmitAtomicExpr()
1347 if (!IsStore) in EmitAtomicExpr()
1351 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1368 if (!IsStore) { in EmitAtomicExpr()
1386 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp823 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
824 if (!IsLoad && !IsStore) in canMoveMemTo()
846 bool Conflict = (L && IsStore) || S; in canMoveMemTo()
H A DHexagonConstExtenders.cpp1146 bool IsStore = MI.mayStore(); in recordExtender() local
1155 if (IsLoad || IsStore) { in recordExtender()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp376 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); in SimplifyShortMoveForm() local
377 unsigned AddrBase = IsStore; in SimplifyShortMoveForm()
378 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm()
H A DX86TargetTransformInfo.cpp3441 bool IsStore = (Instruction::Store == Opcode); in getMaskedMemoryOpCost() local
3452 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment)) || in getMaskedMemoryOpCost()
3464 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); in getMaskedMemoryOpCost()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14846 bool IsStore = false; in performNEONPostLDSTCombine() local
14861 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
14863 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
14865 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
14873 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
14875 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
14877 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
14891 NumVecs = 2; IsStore = true; IsLaneOp = true; break; in performNEONPostLDSTCombine()
14893 NumVecs = 3; IsStore = true; IsLaneOp = true; break; in performNEONPostLDSTCombine()
14895 NumVecs = 4; IsStore = true; IsLaneOp = true; break; in performNEONPostLDSTCombine()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp915 bool IsStore = Opcode == TargetOpcode::G_STORE; in applyCombineIndexedLoadStore() local
935 if (IsStore) { in applyCombineIndexedLoadStore()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp2636 bool IsStore = I.getOpcode() == TargetOpcode::G_STORE; in select() local
2653 IsStore ? NewInst.addUse(ValReg) : NewInst.addDef(ValReg); in select()