| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSERegisterInfo.cpp | 200 bool IsKill = false; in eliminateFI() local
235 IsKill = true; in eliminateFI()
252 IsKill = true; in eliminateFI()
256 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
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| H A D | Mips16RegisterInfo.cpp | 123 bool IsKill = false; in eliminateFI() local
139 IsKill = true; in eliminateFI()
141 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
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| H A D | MipsSEFrameLowering.cpp | 832 bool IsKill = !IsRAAndRetAddrIsTaken; in spillCalleeSavedRegisters() local
834 TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, in spillCalleeSavedRegisters()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kInstrBuilder.h | 50 bool IsKill, int Offset) { in addRegIndirectWithDisp() argument
51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill)); in addRegIndirectWithDisp()
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| H A D | M68kInstrInfo.h | 282 bool IsKill, int FrameIndex,
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| H A D | M68kInstrInfo.cpp | 757 Register SrcReg, bool IsKill, in storeRegToStackSlot() argument
768 .addReg(SrcReg, getKillRegState(IsKill)); in storeRegToStackSlot()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | FixupStatepointCallerSaved.cpp | 116 bool &IsKill, const TargetInstrInfo &TII, in performCopyPropagation() argument
121 IsKill = false; in performCopyPropagation()
158 IsKill = DestSrc->Source->isKill(); in performCopyPropagation()
418 bool IsKill = true; in spillRegisters() local
420 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI); in spillRegisters()
423 TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI, in spillRegisters()
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| H A D | ScheduleDAGInstrs.cpp | 403 bool IsKill = MO.getSubReg() == 0 || MO.isUndef(); in addVRegDefDeps() local
407 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask; in addVRegDefDeps()
1108 bool IsKill = LiveRegs.available(MRI, Reg); in toggleKills() local
1109 MO.setIsKill(IsKill); in toggleKills()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 126 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
135 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
140 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 82 bool IsKill; member
114 IsKill(MI->getOperand(0).isKill()), DL(MI->getDebugLoc()), Index(Index), in SGPRSpillBuilder()
921 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
941 .addReg(Src, getKillRegState(IsKill)); in spillVGPRtoAGPR()
1023 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1154 SrcDstRegState |= getKillRegState(IsKill); in buildSpillLoadStore()
1169 auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill); in buildSpillLoadStore()
1217 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
1232 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
1273 bool IsKill) const { in buildVGPRSpillLoadStore()
[all …]
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| H A D | SIShrinkInstructions.cpp | 245 bool IsKill = NewAddrDwords == Info->VAddrDwords; in shrinkMIMG() local
258 IsKill = false; in shrinkMIMG()
292 MI.getOperand(VAddr0Idx).setIsKill(IsKill); in shrinkMIMG()
367 const bool IsKill = SrcReg->isKill(); in shrinkScalarLogicOp() local
374 /*isImp*/ false, IsKill, in shrinkScalarLogicOp()
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| H A D | SIRegisterInfo.h | 112 bool IsLoad, bool IsKill = true) const;
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| H A D | SIInstrInfo.cpp | 2045 bool IsKill = RegOp.isKill(); in swapRegAndNonRegOperand() local
2063 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug); in swapRegAndNonRegOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1419 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg); in insertCSRSpillsInBlock() local
1422 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI); in insertCSRSpillsInBlock()
1423 if (IsKill) in insertCSRSpillsInBlock()
1782 bool IsKill = MI->getOperand(2).isKill(); in expandStoreInt() local
1791 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1845 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVecPred() local
1860 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1934 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVec2() local
1954 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
1965 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
[all …]
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| H A D | HexagonBlockRanges.cpp | 326 bool IsKill = Op.isKill(); in computeInitialLiveRanges() local
329 if (IsKill) in computeInitialLiveRanges()
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| H A D | HexagonFrameLowering.h | 175 bool IsDef, bool IsKill) const;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 275 unsigned Dst, unsigned Src, bool IsKill) { in insertCopy() argument
278 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
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| H A D | AArch64InstrInfo.cpp | 3579 Register SrcReg, bool IsKill, in storeRegPairToStackSlot() argument
3591 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
3592 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Support/Unix/ |
| H A D | Signals.inc | 298 enum class SignalKind { IsKill, IsInfo };
307 case SignalKind::IsKill:
325 registerHandler(S, SignalKind::IsKill);
327 registerHandler(S, SignalKind::IsKill);
329 registerHandler(SIGPIPE, SignalKind::IsKill);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 57 Register SourceRegister, bool IsKill, int FrameIndex,
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| H A D | LanaiInstrInfo.cpp | 51 Register SourceRegister, bool IsKill, int FrameIndex, in storeRegToStackSlot() argument
63 .addReg(SourceRegister, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 45 bool IsKill, int FrameIndex,
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| H A D | RISCVInstrInfo.cpp | 244 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
314 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
329 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 870 bool IsKill = MO.isKill(); in MergeOpsUpdate() local
871 if (IsKill) in MergeOpsUpdate()
873 Regs.push_back(std::make_pair(Reg, IsKill)); in MergeOpsUpdate()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1279 bool IsKill = MI.getOperand(1).isKill(); in convertToThreeAddressWithLEA() local
1286 .addReg(Src, getKillRegState(IsKill)); in convertToThreeAddressWithLEA()
1357 if (IsKill) in convertToThreeAddressWithLEA()
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