Searched refs:IsAGPR (Results 1 – 6 of 6) sorted by relevance
809 bool IsAGPR = false; in analyzeResourceUsage() local895 IsAGPR = true; in analyzeResourceUsage()907 IsAGPR = true; in analyzeResourceUsage()917 IsAGPR = true; in analyzeResourceUsage()929 IsAGPR = true; in analyzeResourceUsage()939 IsAGPR = true; in analyzeResourceUsage()949 IsAGPR = true; in analyzeResourceUsage()961 IsAGPR = true; in analyzeResourceUsage()973 IsAGPR = true; in analyzeResourceUsage()983 IsAGPR = true; in analyzeResourceUsage()[all …]
262 bool IsAGPR = TRI->hasAGPRs(DstRC); in foldVGPRCopyIntoRegSequence() local281 if (IsAGPR) { in foldVGPRCopyIntoRegSequence()
1043 const bool IsAGPR = !ST.hasGFX90AInsts() && hasAGPRs(RC); in buildSpillLoadStore() local1048 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()1205 if (IsAGPR) { in buildSpillLoadStore()1249 if (!IsAGPR && NeedSuperRegDef) in buildSpillLoadStore()
924 bool IsAGPR = TRI->hasAGPRs(DataRC); in checkAndPrepareMerge() local994 if (TRI->hasAGPRs(getDataRegClass(*MBBI)) != IsAGPR) in checkAndPrepareMerge()1002 if (IsAGPR && CI.InstClass == DS_WRITE) in checkAndPrepareMerge()
3808 const bool IsAGPR = !IsVGPR && RI.hasAGPRs(RC); in verifyInstruction() local3809 if ((IsVGPR || IsAGPR) && MO.getSubReg()) { in verifyInstruction()4678 bool IsAGPR = RI.isAGPR(MRI, MO->getReg()); in isOperandLegal() local4679 if (IsAGPR && !ST.hasMAIInsts()) in isOperandLegal()4682 if (IsAGPR && in isOperandLegal()4692 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isOperandLegal()4696 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isOperandLegal()4702 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isOperandLegal()
1245 bool IsAGPR = Val & 512; in decodeSrcOp() local1249 return createRegOperand(IsAGPR ? getAgprClassId(Width) in decodeSrcOp()