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Searched refs:InstRef (Results 1 – 25 of 30) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
H A DScheduler.h36 virtual bool compare(const InstRef &Lhs, const InstRef &Rhs) const = 0;
43 int computeRank(const InstRef &Lhs) const { in computeRank()
51 bool compare(const InstRef &Lhs, const InstRef &Rhs) const override { in compare()
111 std::vector<InstRef> WaitSet;
112 std::vector<InstRef> PendingSet;
113 std::vector<InstRef> ReadySet;
114 std::vector<InstRef> IssuedSet;
138 InstRef &IR,
144 void updateIssuedSet(SmallVectorImpl<InstRef> &Executed);
149 bool promoteToReadySet(SmallVectorImpl<InstRef> &Ready);
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H A DLSUnit.h49 InstRef CriticalMemoryInstruction;
75 const InstRef &getCriticalMemoryInstruction() const { in getCriticalMemoryInstruction()
115 void onGroupIssued(const InstRef &IR, bool ShouldUpdateCriticalDep) { in onGroupIssued()
135 void onInstructionIssued(const InstRef &IR) { in onInstructionIssued()
163 void onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted()
256 virtual Status isAvailable(const InstRef &IR) const = 0;
264 virtual unsigned dispatch(const InstRef &IR) = 0;
276 bool isReady(const InstRef &IR) const { in isReady()
284 bool isPending(const InstRef &IR) const { in isPending()
292 bool isWaiting(const InstRef &IR) const { in isWaiting()
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H A DRetireControlUnit.h52 InstRef IR;
91 unsigned dispatch(const InstRef &IS);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) { in isAvailable()
71 InstRef &IR, in issueInstructionImpl()
100 InstRef &IR, in issueInstruction()
102 SmallVectorImpl<InstRef> &PendingInstructions, in issueInstruction()
103 SmallVectorImpl<InstRef> &ReadyInstructions) { in issueInstruction()
119 bool Scheduler::promoteToReadySet(SmallVectorImpl<InstRef> &Ready) { in promoteToReadySet()
124 InstRef &IR = *I; in promoteToReadySet()
155 bool Scheduler::promoteToPendingSet(SmallVectorImpl<InstRef> &Pending) { in promoteToPendingSet()
160 InstRef &IR = *I; in promoteToPendingSet()
192 InstRef Scheduler::select() { in select()
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H A DLSUnit.cpp69 unsigned LSUnit::dispatch(const InstRef &IR) { in dispatch()
195 LSUnit::Status LSUnit::isAvailable(const InstRef &IR) const { in isAvailable()
204 void LSUnitBase::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted()
213 void LSUnitBase::onInstructionRetired(const InstRef &IR) { in onInstructionRetired()
232 void LSUnit::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted()
H A DRetireControlUnit.cpp43 unsigned RetireControlUnit::dispatch(const InstRef &IR) { in dispatch()
85 Current = { InstRef(), 0U, false }; in consumeCurrentToken()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DExecuteStage.cpp43 bool ExecuteStage::isAvailable(const InstRef &IR) const { in isAvailable()
53 Error ExecuteStage::issueInstruction(InstRef &IR) { in issueInstruction()
55 SmallVector<InstRef, 4> Pending; in issueInstruction()
56 SmallVector<InstRef, 4> Ready; in issueInstruction()
72 for (const InstRef &I : Pending) in issueInstruction()
75 for (const InstRef &I : Ready) in issueInstruction()
81 InstRef IR = HWS.select(); in issueReadyInstructions()
95 SmallVector<InstRef, 4> Executed; in cycleStart()
96 SmallVector<InstRef, 4> Pending; in cycleStart()
97 SmallVector<InstRef, 4> Ready; in cycleStart()
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H A DInOrderIssueStage.cpp35 bool InOrderIssueStage::isAvailable(const InstRef &IR) const { in isAvailable()
55 static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) { in hasResourceHazard()
64 static unsigned findLastWriteBackCycle(const InstRef &IR) { in findLastWriteBackCycle()
77 static unsigned findFirstWriteBackCycle(const InstRef &IR) { in findFirstWriteBackCycle()
95 const InstRef &IR) { in checkRegisterHazard()
144 bool InOrderIssueStage::canExecute(const InstRef &IR, in canExecute()
190 const InstRef &IR, in notifyInstructionIssue()
201 static void notifyInstructionDispatch(const InstRef &IR, unsigned Ops, in notifyInstructionDispatch()
211 llvm::Error InOrderIssueStage::execute(InstRef &IR) { in execute()
222 llvm::Error InOrderIssueStage::tryIssue(InstRef &IR, unsigned *StallCycles) { in tryIssue()
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H A DDispatchStage.cpp38 void DispatchStage::notifyInstructionDispatched(const InstRef &IR, in notifyInstructionDispatched()
46 bool DispatchStage::checkPRF(const InstRef &IR) const { in checkPRF()
62 bool DispatchStage::checkRCU(const InstRef &IR) const { in checkRCU()
71 bool DispatchStage::canDispatch(const InstRef &IR) const { in canDispatch()
78 Error DispatchStage::dispatch(InstRef IR) { in dispatch()
151 CarriedOver = InstRef(); in cycleStart()
155 bool DispatchStage::isAvailable(const InstRef &IR) const { in isAvailable()
176 Error DispatchStage::execute(InstRef &IR) { in execute()
H A DEntryStage.cpp25 bool EntryStage::isAvailable(const InstRef & /* unused */) const { in isAvailable()
37 CurrentInstruction = InstRef(SR.first, Inst.get()); in getNextInstruction()
42 llvm::Error EntryStage::execute(InstRef & /*unused */) { in execute() argument
H A DMicroOpQueueStage.cpp22 InstRef IR = Buffer[CurrentInstructionSlotIdx]; in moveInstructions()
46 Error MicroOpQueueStage::execute(InstRef &IR) { in execute()
H A DRetireStage.cpp49 llvm::Error RetireStage::execute(InstRef &IR) { in execute()
60 void RetireStage::notifyInstructionRetired(const InstRef &IR) const { in notifyInstructionRetired()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/
H A DExecuteStage.h37 Error issueInstruction(InstRef &IR);
44 Error handleInstructionEliminated(InstRef &IR);
62 bool isAvailable(const InstRef &IR) const override;
73 Error execute(InstRef &IR) override;
76 const InstRef &IR,
78 void notifyInstructionExecuted(const InstRef &IR) const;
79 void notifyInstructionPending(const InstRef &IR) const;
80 void notifyInstructionReady(const InstRef &IR) const;
84 void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
H A DDispatchStage.h53 InstRef CarriedOver;
58 bool checkRCU(const InstRef &IR) const;
59 bool checkPRF(const InstRef &IR) const;
60 bool canDispatch(const InstRef &IR) const;
61 Error dispatch(InstRef IR);
63 void notifyInstructionDispatched(const InstRef &IR,
72 bool isAvailable(const InstRef &IR) const override;
78 Error execute(InstRef &IR) override;
H A DInOrderIssueStage.h38 SmallVector<InstRef, 4> IssuedInst;
45 InstRef StalledInst;
49 InstRef CarriedOver;
67 bool canExecute(const InstRef &IR, unsigned *StallCycles) const;
70 Error tryIssue(InstRef &IR, unsigned *StallCycles);
79 void retireInstruction(InstRef &IR);
88 bool isAvailable(const InstRef &) const override;
90 Error execute(InstRef &IR) override;
H A DStage.h25 class InstRef; variable
42 virtual bool isAvailable(const InstRef &IR) const { return true; } in isAvailable()
55 virtual Error execute(InstRef &IR) = 0;
62 bool checkNextStage(const InstRef &IR) const { in checkNextStage()
70 Error moveToTheNextStage(InstRef &IR) { in moveToTheNextStage()
H A DMicroOpQueueStage.h27 SmallVector<InstRef, 8> Buffer;
54 unsigned getNormalizedOpcodes(const InstRef &IR) const { in getNormalizedOpcodes()
67 bool isAvailable(const InstRef &IR) const override { in isAvailable()
80 Error execute(InstRef &IR) override;
H A DEntryStage.h27 InstRef CurrentInstruction;
41 bool isAvailable(const InstRef &IR) const override;
43 Error execute(InstRef &IR) override;
H A DRetireStage.h44 Error execute(InstRef &IR) override;
45 void notifyInstructionRetired(const InstRef &IR) const;
H A DInstructionTables.h40 Error execute(InstRef &IR) override;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DHWEventListener.h52 HWInstructionEvent(unsigned type, const InstRef &Inst) in HWInstructionEvent()
59 const InstRef &IR;
65 HWInstructionIssuedEvent(const InstRef &IR, in HWInstructionIssuedEvent()
74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
120 HWStallEvent(unsigned type, const InstRef &Inst) : Type(type), IR(Inst) {} in HWStallEvent()
126 const InstRef &IR;
144 HWPressureEvent(GenericReason reason, ArrayRef<InstRef> Insts,
152 ArrayRef<InstRef> AffectedInstructions;
173 virtual void onReservedBuffers(const InstRef &Inst, in onReservedBuffers()
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H A DInstruction.h563 class InstRef {
567 InstRef() : Data(std::make_pair(0, nullptr)) {} in InstRef() function
568 InstRef(unsigned Index, Instruction *I) : Data(std::make_pair(Index, I)) {} in InstRef() function
570 bool operator==(const InstRef &Other) const { return Data == Other.Data; }
571 bool operator!=(const InstRef &Other) const { return Data != Other.Data; }
572 bool operator<(const InstRef &Other) const {
592 inline raw_ostream &operator<<(raw_ostream &OS, const InstRef &IR) {
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
H A DSchedulerStatistics.h82 void onReservedBuffers(const InstRef &IR,
87 void onReleasedBuffers(const InstRef &IR,
H A DSchedulerStatistics.cpp74 void SchedulerStatistics::onReservedBuffers(const InstRef & /* unused */, in onReservedBuffers() argument
83 void SchedulerStatistics::onReleasedBuffers(const InstRef & /* unused */, in onReleasedBuffers() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
H A DVPlanHCFGBuilder.cpp197 for (Instruction &InstRef : *BB) { in createVPInstructionsForVPBB()
198 Instruction *Inst = &InstRef; in createVPInstructionsForVPBB()

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