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Searched refs:Insn (Results 1 – 25 of 146) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp45 uint64_t &Size, uint16_t &Insn) { in readInstruction16() argument
52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
57 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
64 Insn = in readInstruction32()
92 unsigned Insn,
97 unsigned Insn,
102 unsigned Insn,
107 unsigned Insn,
112 unsigned Insn,
117 unsigned Insn,
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp98 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn,
101 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn,
104 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
107 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
110 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
113 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn,
116 static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
119 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
122 static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn,
125 static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp251 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
253 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
256 unsigned Insn,
259 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
261 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
263 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
265 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
269 unsigned Insn,
272 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
274 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp54 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
57 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
60 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
63 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
70 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
76 uint32_t &Insn) { in readInstruction32() argument
84 Insn = in readInstruction32()
90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
101 AluOp = (Insn >> 8) & 0x7; in PostOperandDecodeAdjust()
105 AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1); in PostOperandDecodeAdjust()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp113 unsigned Insn,
147 unsigned Insn,
217 unsigned Insn,
267 unsigned Insn,
274 unsigned Insn,
279 unsigned Insn,
284 unsigned Insn,
289 unsigned Insn,
293 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
297 unsigned Insn,
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp51 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
54 Insn = in readInstruction32()
60 uint64_t &Size, uint64_t &Insn) { in readInstruction64() argument
62 Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) | in readInstruction64()
70 uint64_t &Size, uint64_t &Insn) { in readInstruction48() argument
72 Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | in readInstruction48()
79 uint64_t &Size, uint32_t &Insn) { in readInstruction16() argument
81 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
145 static unsigned decodeCField(unsigned Insn) { in decodeCField() argument
146 return fieldFromInstruction(Insn, 6, 6); in decodeCField()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp44 SmallVectorImpl<ImmInsnModel> &Insn) { in tryToreplicateChunks() argument
68 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in tryToreplicateChunks()
81 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
96 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
152 SmallVectorImpl<ImmInsnModel> &Insn) { in trySequenceOfOnes() argument
224 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in trySequenceOfOnes()
227 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx), in trySequenceOfOnes()
236 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx), in trySequenceOfOnes()
247 SmallVectorImpl<ImmInsnModel> &Insn) { in expandMOVImmSimple() argument
279 Insn.push_back({ FirstOpc, Imm16, in expandMOVImmSimple()
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H A DAArch64ExpandImm.h29 SmallVectorImpl<ImmInsnModel> &Insn);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp181 static AddrMode DecodeSrcAddrModeI(unsigned Insn) { in DecodeSrcAddrModeI() argument
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI()
183 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeI()
187 static AddrMode DecodeSrcAddrModeII(unsigned Insn) { in DecodeSrcAddrModeII() argument
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII()
189 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeII()
193 static AddrMode DecodeDstAddrMode(unsigned Insn) { in DecodeDstAddrMode() argument
194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode()
195 unsigned Ad = fieldFromInstruction(Insn, 7, 1); in DecodeDstAddrMode()
233 uint64_t Insn = support::endian::read16le(Bytes.data()); in getInstructionI() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DInstructionPrecedenceTracking.cpp59 const Instruction *Insn) { in isPreceededBySpecialInstruction() argument
61 getFirstSpecialInstruction(Insn->getParent()); in isPreceededBySpecialInstruction()
62 return MaybeFirstSpecial && MaybeFirstSpecial->comesBefore(Insn); in isPreceededBySpecialInstruction()
84 for (const Instruction &Insn : *BB) in validate()
85 if (isSpecialInstruction(&Insn)) { in validate()
86 assert(It->second == &Insn && in validate()
130 const Instruction *Insn) const { in isSpecialInstruction()
136 return !isGuaranteedToTransferExecutionToSuccessor(Insn); in isSpecialInstruction()
140 const Instruction *Insn) const { in isSpecialInstruction()
142 if (match(Insn, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) in isSpecialInstruction()
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H A DGuardUtils.cpp35 for (auto &Insn : *DeoptBB) { in isGuardAsWidenableBranch()
36 if (match(&Insn, m_Intrinsic<Intrinsic::experimental_deoptimize>())) in isGuardAsWidenableBranch()
38 if (Insn.mayHaveSideEffects()) in isGuardAsWidenableBranch()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp55 CodeGenInstruction &Insn,
73 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, in addDagOperandMapping() argument
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) { in addDagOperandMapping()
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); in addDagOperandMapping()
104 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) in addDagOperandMapping()
106 OpsAdded += Insn.Operands[i].MINumOperands; in addDagOperandMapping()
120 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); in addDagOperandMapping()
155 CodeGenInstruction Insn(Operator); in evaluateExpansion() local
157 if (Insn.isCodeGenOnly || Insn.isPseudo) { in evaluateExpansion()
165 if (Insn.Operands.size() != Dag->getNumArgs()) { in evaluateExpansion()
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H A DFixedLenDecoderEmitter.cpp422 void insnWithID(insn_t &Insn, unsigned Opcode) const { in insnWithID() argument
435 Insn.push_back(BIT_UNSET); in insnWithID()
437 Insn.push_back(bitFromBits(Bits, i)); in insnWithID()
455 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit,
483 const insn_t &Insn) const;
564 insn_t Insn; in Filter() local
567 Owner->insnWithID(Insn, Owner->Opcodes[i].EncodingID); in Filter()
571 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits); in Filter()
1001 bool FilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn, in fieldFromInsn() argument
1006 if (Insn[StartBit + i] == BIT_UNSET) in fieldFromInsn()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp340 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
343 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
346 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
350 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
353 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
359 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, in decodeRVCInstrSImm() argument
362 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrSImm()
369 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, in decodeRVCInstrRdSImm() argument
374 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdSImm()
381 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, in decodeRVCInstrRdRs1UImm() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
H A DInstructionPrecedenceTracking.h62 bool isPreceededBySpecialInstruction(const Instruction *Insn);
69 virtual bool isSpecialInstruction(const Instruction *Insn) const = 0;
114 bool isDominatedByICFIFromSameBlock(const Instruction *Insn) { in isDominatedByICFIFromSameBlock() argument
115 return isPreceededBySpecialInstruction(Insn); in isDominatedByICFIFromSameBlock()
118 bool isSpecialInstruction(const Instruction *Insn) const override;
137 bool isDominatedByMemoryWriteFromSameBlock(const Instruction *Insn) { in isDominatedByMemoryWriteFromSameBlock() argument
138 return isPreceededBySpecialInstruction(Insn); in isDominatedByMemoryWriteFromSameBlock()
141 bool isSpecialInstruction(const Instruction *Insn) const override;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp126 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, in decodeMemoryOpValue() argument
128 unsigned Register = (Insn >> 16) & 0xf; in decodeMemoryOpValue()
133 unsigned Offset = (Insn & 0xffff); in decodeMemoryOpValue()
141 uint64_t &Size, uint64_t &Insn, in readInstruction64() argument
159 Insn = Make_64(Hi, Lo); in readInstruction64()
169 uint64_t Insn, Hi; in getInstruction() local
172 Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian); in getInstruction()
175 uint8_t InstClass = getInstClass(Insn); in getInstruction()
176 uint8_t InstMode = getInstMode(Insn); in getInstruction()
178 getInstSize(Insn) != BPF_DW && in getInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldELFMips.cpp215 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); in applyMIPSRelocation() local
233 Insn = (Insn & 0xffff0000) | (Value & 0x0000ffff); in applyMIPSRelocation()
234 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
237 Insn = (Insn & 0xfffc0000) | (Value & 0x0003ffff); in applyMIPSRelocation()
238 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
241 Insn = (Insn & 0xfff80000) | (Value & 0x0007ffff); in applyMIPSRelocation()
242 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
245 Insn = (Insn & 0xffe00000) | (Value & 0x001fffff); in applyMIPSRelocation()
246 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
250 Insn = (Insn & 0xfc000000) | (Value & 0x03ffffff); in applyMIPSRelocation()
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H A DRuntimeDyldMachOARM.h272 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); in resolveRelocation() local
275 Insn = (Insn & 0x8f00fbf0) | ((Value & 0xf000) >> 12) | in resolveRelocation()
279 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff); in resolveRelocation()
280 writeBytesUnaligned(Insn, LocalAddress, 4); in resolveRelocation()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp1720 InternalInstruction Insn; in getInstruction() local
1721 memset(&Insn, 0, sizeof(InternalInstruction)); in getInstruction()
1722 Insn.bytes = Bytes; in getInstruction()
1723 Insn.startLocation = Address; in getInstruction()
1724 Insn.readerCursor = Address; in getInstruction()
1725 Insn.mode = fMode; in getInstruction()
1727 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) || in getInstruction()
1728 getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 || in getInstruction()
1729 readOperands(&Insn)) { in getInstruction()
1730 Size = Insn.readerCursor - Address; in getInstruction()
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/netbsd-src/external/gpl3/binutils/dist/gold/
H A Dpowerpc.cc10668 typedef typename elfcpp::Swap<32, big_endian>::Valtype Insn; in relocate() typedef
10698 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10703 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10709 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10880 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10888 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
11014 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
11030 Insn* iview = reinterpret_cast<Insn*>(view - d_offset); in relocate()
11031 Insn insn = elfcpp::Swap<32, big_endian>::readval(iview); in relocate()
11047 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
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/netbsd-src/external/gpl3/binutils.old/dist/gold/
H A Dpowerpc.cc10617 typedef typename elfcpp::Swap<32, big_endian>::Valtype Insn; in relocate() typedef
10647 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10652 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10658 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10834 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10842 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10968 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
10984 Insn* iview = reinterpret_cast<Insn*>(view - d_offset); in relocate()
10985 Insn insn = elfcpp::Swap<32, big_endian>::readval(iview); in relocate()
11001 Insn* iview = reinterpret_cast<Insn*>(view); in relocate()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp340 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); in findPltEntries() local
343 if (Insn == 0xd503245f) { in findPltEntries()
345 Insn = support::endian::read32le(PltContents.data() + Byte + Off); in findPltEntries()
348 if ((Insn & 0x9f000000) != 0x90000000) in findPltEntries()
352 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14); in findPltEntries()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp314 uint64_t &Size, uint32_t &Insn, in readInstruction32() argument
322 Insn = IsLittleEndian in readInstruction32()
335 uint32_t Insn; in getInstruction() local
338 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); in getInstruction()
346 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); in getInstruction()
350 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); in getInstruction()
356 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); in getInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DGVNHoist.cpp645 Instruction *Insn = MU->getMemoryInst(); in hasMemoryUse() local
648 if (BB == OldBB && firstInBB(OldPt, Insn)) in hasMemoryUse()
654 if (firstInBB(Insn, NewPt)) in hasMemoryUse()
810 Instruction *Insn = CHI.I; in checkSafety() local
811 if (!Insn) // No instruction was inserted in this CHI. in checkSafety()
814 if (safeToHoistScalar(BB, Insn->getParent(), NumBBsOnAllPaths)) in checkSafety()
818 if (MemoryUseOrDef *UD = MSSA->getMemoryAccess(Insn)) in checkSafety()
819 if (safeToHoistLdSt(T, Insn, UD, K, NumBBsOnAllPaths)) in checkSafety()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td113 let TSFlags{23} = isExtendable; // Insn may be extended.
115 let TSFlags{24} = isExtended; // Insn must be extended.
317 let TSFlags{17} = isExtendable; // Insn may be extended.
319 let TSFlags{18} = isExtended; // Insn must be extended.

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