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Searched refs:InsInstrs (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineCombiner.cpp96 unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
104 SmallVectorImpl<MachineInstr *> &InsInstrs,
109 SmallVectorImpl<MachineInstr *> &InsInstrs,
114 SmallVectorImpl<MachineInstr *> &InsInstrs,
120 SmallVectorImpl<MachineInstr *> &InsInstrs,
171 MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs, in getDepth() argument
181 for (auto *InstrPtr : InsInstrs) { // for each Use in getDepth()
196 MachineInstr *DefInstr = InsInstrs[II->second]; in getDepth()
217 unsigned NewRootIdx = InsInstrs.size() - 1; in getDepth()
295 MachineInstr &MI, SmallVectorImpl<MachineInstr *> &InsInstrs, in getLatenciesForInstrSequences() argument
[all …]
H A DTargetInstrInfo.cpp810 SmallVectorImpl<MachineInstr *> &InsInstrs, in reassociateOps() argument
885 InsInstrs.push_back(MIB1); in reassociateOps()
886 InsInstrs.push_back(MIB2); in reassociateOps()
893 SmallVectorImpl<MachineInstr *> &InsInstrs, in genAlternativeCodeSequence() argument
915 reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg); in genAlternativeCodeSequence()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp5006 SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd, in genFusedMultiply() argument
5060 InsInstrs.push_back(MIB); in genFusedMultiply()
5070 MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, in genFusedMultiplyAcc() argument
5072 return genFusedMultiply(MF, MRI, TII, Root, InsInstrs, IdxMulOpd, MaddOpc, RC, in genFusedMultiplyAcc()
5080 SmallVectorImpl<MachineInstr *> &InsInstrs, in genNeg() argument
5087 InsInstrs.push_back(MIB); in genNeg()
5099 MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, in genFusedMultiplyAccNeg() argument
5105 genNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, MnegOpc, RC); in genFusedMultiplyAccNeg()
5106 return genFusedMultiply(MF, MRI, TII, Root, InsInstrs, IdxMulOpd, MaddOpc, RC, in genFusedMultiplyAccNeg()
5116 MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, in genFusedMultiplyIdx() argument
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H A DAArch64InstrInfo.h257 SmallVectorImpl<MachineInstr *> &InsInstrs,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h252 SmallVectorImpl<MachineInstr *> &InsInstrs,
258 SmallVectorImpl<MachineInstr *> &InsInstrs) const;
343 SmallVectorImpl<MachineInstr *> &InsInstrs,
373 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
H A DPPCInstrInfo.cpp545 SmallVectorImpl<MachineInstr *> &InsInstrs) const { in finalizeInsInstrs()
546 assert(!InsInstrs.empty() && "Instructions set to be inserted is empty!"); in finalizeInsInstrs()
592 for (auto *Inst : InsInstrs) { in finalizeInsInstrs()
607 generateLoadForNewConst(ConstPoolIdx, &Root, C->getType(), InsInstrs); in finalizeInsInstrs()
687 SmallVectorImpl<MachineInstr *> &InsInstrs) const { in generateLoadForNewConst()
731 InsInstrs.insert(InsInstrs.begin(), Load); in generateLoadForNewConst()
732 InsInstrs.insert(InsInstrs.begin(), TOCOffset); in generateLoadForNewConst()
776 SmallVectorImpl<MachineInstr *> &InsInstrs, in genAlternativeCodeSequence() argument
784 reassociateFMA(Root, Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg); in genAlternativeCodeSequence()
788 TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs, in genAlternativeCodeSequence()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1119 SmallVectorImpl<MachineInstr *> &InsInstrs) const {} in finalizeInsInstrs() argument
1157 SmallVectorImpl<MachineInstr *> &InsInstrs,
1165 SmallVectorImpl<MachineInstr *> &InsInstrs,