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Searched refs:InitReg (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DModuloSchedule.cpp1272 Register phi(Register LoopReg, Optional<Register> InitReg = {},
1457 Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg, in phi() argument
1460 if (InitReg.hasValue()) { in phi()
1461 auto I = Phis.find({LoopReg, InitReg.getValue()}); in phi()
1476 if (!InitReg.hasValue()) in phi()
1482 MI->getOperand(1).setReg(InitReg.getValue()); in phi()
1483 Phis.insert({{LoopReg, InitReg.getValue()}, R}); in phi()
1484 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue())); in phi()
1493 if (InitReg.hasValue()) in phi()
1494 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDILCFGStructurizer.cpp1295 Register InitReg = in improveSimpleJumpintoIf() local
1297 insertCondBranchBefore(LandBlk, I, R600::IF_PREDICATE_SET, InitReg, in improveSimpleJumpintoIf()
H A DAMDGPURegisterBankInfo.cpp744 Register InitReg = B.buildUndef(ResTy).getReg(0); in executeInWaterfallLoop() local
746 InitResultRegs.push_back(InitReg); in executeInWaterfallLoop()
749 MRI.setRegBank(InitReg, *DefBank); in executeInWaterfallLoop()
H A DSIISelLowering.cpp3496 unsigned InitReg, unsigned ResultReg, unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
3512 .addReg(InitReg) in emitLoadM0FromVGPRLoop()
3744 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitIndirectSrc() local
3746 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg); in emitIndirectSrc()
3749 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset, in emitIndirectSrc()