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Searched refs:IndexReg (Results 1 – 25 of 27) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp385 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
395 if (IndexReg != 0) in optTwoAddrLEA()
396 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optTwoAddrLEA()
403 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
404 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
407 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
412 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
417 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
419 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
570 Register IndexReg = Index.getReg(); in processInstrForSlow3OpLEA() local
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H A DX86InstrBuilder.h54 unsigned IndexReg; member
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
108 AM.IndexReg = Op2.getReg(); in getAddressFromInstr()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
H A DX86InsertPrefetch.cpp83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
87 (IndexReg == 0 || in IsMemOpCompatibleWithPrefetch()
88 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) || in IsMemOpCompatibleWithPrefetch()
89 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)); in IsMemOpCompatibleWithPrefetch()
H A DX86AsmPrinter.cpp289 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
299 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
320 assert(IndexReg.getReg() != X86::ESP && in PrintLeaMemReference()
327 if (IndexReg.getReg()) { in PrintLeaMemReference()
355 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
379 if (IndexReg.getReg()) { in PrintIntelMemReference()
392 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
H A DX86FastISel.cpp226 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
737 (AM.Base.Reg == 0 && AM.IndexReg == 0)) { in handleConstantAddresses()
756 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in handleConstantAddresses()
818 if (AM.IndexReg == 0) { in handleConstantAddresses()
820 AM.IndexReg = getRegForValue(V); in handleConstantAddresses()
821 return AM.IndexReg != 0; in handleConstantAddresses()
905 unsigned IndexReg = AM.IndexReg; in X86SelectAddress() local
937 if (IndexReg == 0 && in X86SelectAddress()
942 IndexReg = getRegForGEPIndex(Op); in X86SelectAddress()
943 if (IndexReg == 0) in X86SelectAddress()
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H A DX86ISelDAGToDAG.cpp69 SDValue IndexReg; member
83 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
94 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
125 if (IndexReg.getNode()) in dump()
126 IndexReg.getNode()->dump(DAG); in dump()
283 AM.IndexReg), 0); in getAddressOperands()
284 AM.IndexReg = Neg; in getAddressOperands()
287 if (AM.IndexReg.getNode()) in getAddressOperands()
288 Index = AM.IndexReg; in getAddressOperands()
1739 AM.Base_Reg.getNode() != nullptr && AM.IndexReg.getNode() == nullptr) { in matchAddress()
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H A DX86SpeculativeLoadHardening.cpp1344 unsigned BaseReg = 0, IndexReg = 0; in tracePredStateThroughBlocksAndHarden() local
1349 IndexReg = IndexMO.getReg(); in tracePredStateThroughBlocksAndHarden()
1351 if (!BaseReg && !IndexReg) in tracePredStateThroughBlocksAndHarden()
1360 (IndexReg && LoadDepRegs.test(IndexReg))) in tracePredStateThroughBlocksAndHarden()
1373 !HardenedAddrRegs.count(IndexReg)) { in tracePredStateThroughBlocksAndHarden()
1384 if (IndexReg) in tracePredStateThroughBlocksAndHarden()
1385 HardenedAddrRegs.insert(IndexReg); in tracePredStateThroughBlocksAndHarden()
H A DX86MCInstLower.cpp1112 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in emitNop() local
1113 IndexReg = Displacement = SegmentReg = 0; in emitNop()
1141 IndexReg = X86::RAX; in emitNop()
1147 IndexReg = X86::RAX; in emitNop()
1158 IndexReg = X86::RAX; in emitNop()
1164 IndexReg = X86::RAX; in emitNop()
1170 IndexReg = X86::RAX; in emitNop()
1194 .addReg(IndexReg) in emitNop()
H A DX86InstructionSelector.cpp617 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in selectGlobalValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp426 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon301d74170111::X86AsmParser::IntelExprStateMachine
450 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), in IntelExprStateMachine()
460 unsigned getIndexReg() const { return IndexReg; } in getIndexReg()
658 if (IndexReg) { in onPlus()
662 IndexReg = TmpReg; in onPlus()
719 if (IndexReg) { in onMinus()
723 IndexReg = TmpReg; in onMinus()
780 if (IndexReg) { in onRegister()
785 IndexReg = Reg; in onRegister()
864 if (IndexReg) { in onInteger()
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H A DX86Operand.h62 unsigned IndexReg; member
136 if (Mem.IndexReg) in print()
138 << X86IntelInstPrinter::getRegisterName(Mem.IndexReg); in print()
192 return Mem.IndexReg; in getMemIndexReg()
325 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
672 Res->Mem.IndexReg = 0;
686 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
693 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
704 Res->Mem.IndexReg = IndexReg;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp69 SDValue IndexReg; member
83 : AM(AT), BaseType(Base::RegBase), Disp(0), BaseFrameIndex(0), IndexReg(), in M68kISelAddressMode()
103 return BaseType == Base::RegBase && IndexReg.getNode() != nullptr; in hasIndexReg()
147 void setIndexReg(SDValue Reg) { IndexReg = Reg; } in setIndexReg()
160 if (IndexReg.getNode()) { in dump()
161 IndexReg.getNode()->dump(); in dump()
374 AM.IndexReg = N; in matchAddressBase()
510 AM.IndexReg = N.getOperand(1); in matchADD()
738 if (!isAddressBase(AM.BaseReg) && isAddressBase(AM.IndexReg)) { in SelectARII()
739 Base = AM.IndexReg; in SelectARII()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp167 unsigned IndexReg = Index.getReg(); in is16BitMemOperand() local
169 if (STI.hasFeature(X86::Mode16Bit) && BaseReg == 0 && IndexReg == 0) in is16BitMemOperand()
173 (IndexReg != 0 && in is16BitMemOperand()
174 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))) in is16BitMemOperand()
184 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand() local
188 (IndexReg.getReg() != 0 && in is32BitMemOperand()
189 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in is32BitMemOperand()
192 assert(IndexReg.getReg() == 0 && "Invalid eip-based address."); in is32BitMemOperand()
195 if (IndexReg.getReg() == X86::EIZ) in is32BitMemOperand()
206 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is64BitMemOperand() local
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H A DX86ATTInstPrinter.cpp399 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
409 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
416 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
421 if (IndexReg.getReg()) { in printMemReference()
H A DX86IntelInstPrinter.cpp357 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
371 if (IndexReg.getReg()) { in printMemReference()
385 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
H A DX86MCTargetDesc.cpp544 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress() local
547 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || in evaluateMemoryOperandAddress()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h67 StringRef IndexReg; member
72 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()), in IntelExpr()
77 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
83 bool hasIndexReg() const { return !IndexReg.empty(); } in hasIndexReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp182 unsigned IndexReg; member
364 return Mem.IndexReg; in getMemIndexReg()
695 Op->Mem.IndexReg = 0; in MorphToMEMri()
706 Op->Mem.IndexReg = 0; in MorphToMEMzi()
717 Op->Mem.IndexReg = Index; in MorphToMEMrri()
729 Op->Mem.IndexReg = 0; in MorphToMEMrii()
740 Op->Mem.IndexReg = Index; in MorphToMEMzri()
751 Op->Mem.IndexReg = 0; in MorphToMEMzii()
1213 unsigned IndexReg = 0; in parseMEMOperand() local
1217 if (ParseRegister(IndexReg, S, E)) in parseMEMOperand()
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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp271 for (const unsigned IndexReg : PossibleIndexRegs.set_bits()) { in generateLEATemplatesCommon() local
279 setMemOp(IT, 3, MCOperand::createReg(IndexReg)); in generateLEATemplatesCommon()
286 RestrictDestRegs(BaseReg, IndexReg, PossibleDestRegsNow); in generateLEATemplatesCommon()
297 RegInfo.getName(IndexReg), Scale, Disp) in generateLEATemplatesCommon()
334 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
394 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
400 State.getRATC().getRegister(IndexReg).aliasedBits()); in generateCodeTemplates()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp167 unsigned &IndexReg);
421 unsigned &IndexReg) { in PPCSimplifyAddress() argument
442 IndexReg = PPCMaterializeInt(Offset, MVT::i64); in PPCSimplifyAddress()
443 assert(IndexReg && "Unexpected error in PPCMaterializeInt!"); in PPCSimplifyAddress()
506 unsigned IndexReg = 0; in PPCEmitLoad() local
507 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitLoad()
579 if (IndexReg) in PPCEmitLoad()
580 MIB.addReg(Addr.Base.Reg).addReg(IndexReg); in PPCEmitLoad()
655 unsigned IndexReg = 0; in PPCEmitStore() local
656 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitStore()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp229 Register IndexReg) { in buildBrJT() argument
235 .addUse(IndexReg); in buildBrJT()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h769 Register IndexReg);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp871 bool IndexReg; member
874 LongDisplacement(LongDispl), IndexReg(IdxReg) {} in AddressingMode()
980 if (!SupportedAM.IndexReg) in isLegalAddressingMode()
7267 Register IndexReg = MI.getOperand(3).getReg(); in emitCondStore() local
7286 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) { in emitCondStore()
7334 .addReg(IndexReg) in emitCondStore()
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DCodeGenerator.rst2221 SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
2230 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/MCParser/
H A DAsmParser.cpp6080 << AR.IntelExp.IndexReg; in parseMSInlineAsm()

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