| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 306 SDValue InOp = N->getOperand(0); in ScalarizeVecRes_BUILD_VECTOR() local
310 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); in ScalarizeVecRes_BUILD_VECTOR()
311 return InOp; in ScalarizeVecRes_BUILD_VECTOR()
433 SDValue InOp = N->getOperand(0); in ScalarizeVecRes_SCALAR_TO_VECTOR() local
434 if (InOp.getValueType() != EltVT) in ScalarizeVecRes_SCALAR_TO_VECTOR()
435 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); in ScalarizeVecRes_SCALAR_TO_VECTOR()
436 return InOp; in ScalarizeVecRes_SCALAR_TO_VECTOR()
1167 SDValue InOp = N->getOperand(0); in SplitVecRes_BITCAST() local
1168 EVT InVT = InOp.getValueType(); in SplitVecRes_BITCAST()
1186 GetExpandedOp(InOp, Lo, Hi); in SplitVecRes_BITCAST()
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| H A D | LegalizeTypesGeneric.cpp | 43 SDValue InOp = N->getOperand(0); in ExpandRes_BITCAST() local
44 EVT InVT = InOp.getValueType(); in ExpandRes_BITCAST()
57 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi); in ExpandRes_BITCAST()
65 GetExpandedOp(InOp, Lo, Hi); in ExpandRes_BITCAST()
74 GetSplitVector(InOp, Lo, Hi); in ExpandRes_BITCAST()
82 SplitInteger(BitConvertToInteger(GetScalarizedVector(InOp)), Lo, Hi); in ExpandRes_BITCAST()
90 InOp = GetWidenedVector(InOp); in ExpandRes_BITCAST()
93 std::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoVT, HiVT); in ExpandRes_BITCAST()
121 SDValue CastInOp = DAG.getNode(ISD::BITCAST, dl, NVT, InOp); in ExpandRes_BITCAST()
171 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, StackPtr, PtrInfo); in ExpandRes_BITCAST()
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| H A D | LegalizeIntegerTypes.cpp | 336 SDValue InOp = N->getOperand(0); in PromoteIntRes_BITCAST() local
337 EVT InVT = InOp.getValueType(); in PromoteIntRes_BITCAST()
349 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
353 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
356 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp)); in PromoteIntRes_BITCAST()
360 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
370 BitConvertToInteger(GetScalarizedVector(InOp))); in PromoteIntRes_BITCAST()
386 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
390 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
400 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
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| H A D | LegalizeTypes.h | 981 SDValue ModifyToType(SDValue InOp, EVT NVT, bool FillWithZeroes = false);
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| H A D | DAGCombiner.cpp | 18535 SDValue InOp = VecOp.getOperand(0); in visitEXTRACT_VECTOR_ELT() local
18536 if (InOp.getValueType() != ScalarVT) { in visitEXTRACT_VECTOR_ELT()
18537 assert(InOp.getValueType().isInteger() && ScalarVT.isInteger()); in visitEXTRACT_VECTOR_ELT()
18538 return DAG.getSExtOrTrunc(InOp, DL, ScalarVT); in visitEXTRACT_VECTOR_ELT()
18540 return InOp; in visitEXTRACT_VECTOR_ELT()
18643 SDValue InOp = SVInVec.getOperand(OrigElt); in visitEXTRACT_VECTOR_ELT() local
18644 if (InOp.getValueType() != ScalarVT) { in visitEXTRACT_VECTOR_ELT()
18645 assert(InOp.getValueType().isInteger() && ScalarVT.isInteger()); in visitEXTRACT_VECTOR_ELT()
18646 InOp = DAG.getSExtOrTrunc(InOp, DL, ScalarVT); in visitEXTRACT_VECTOR_ELT()
18649 return InOp; in visitEXTRACT_VECTOR_ELT()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXProxyRegErasure.cpp | 96 auto &InOp = *MI.uses().begin(); in replaceMachineInstructionUsage() local
99 assert(InOp.isReg() && "ProxyReg input operand should be a register."); in replaceMachineInstructionUsage()
104 replaceRegisterUsage(I, OutOp, InOp); in replaceMachineInstructionUsage()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3752 SDValue InOp = Op.getOperand(1); in lowerConvertToSVBool() local
3753 EVT InVT = InOp.getValueType(); in lowerConvertToSVBool()
3758 return InOp; in lowerConvertToSVBool()
3761 DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, OutVT, InOp); in lowerConvertToSVBool()
3765 switch (InOp.getOpcode()) { in lowerConvertToSVBool()
3769 if (InOp.getConstantOperandVal(0) == Intrinsic::aarch64_sve_ptrue) in lowerConvertToSVBool()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 29927 static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG, in ExtendToType() argument
29930 MVT InVT = InOp.getSimpleValueType(); in ExtendToType()
29932 return InOp; in ExtendToType()
29934 if (InOp.isUndef()) in ExtendToType()
29945 SDLoc dl(InOp); in ExtendToType()
29946 if (InOp.getOpcode() == ISD::CONCAT_VECTORS && in ExtendToType()
29947 InOp.getNumOperands() == 2) { in ExtendToType()
29948 SDValue N1 = InOp.getOperand(1); in ExtendToType()
29951 InOp = InOp.getOperand(0); in ExtendToType()
29952 InVT = InOp.getSimpleValueType(); in ExtendToType()
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