Searched refs:HiLHS (Results 1 – 4 of 4) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 653 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping() local
656 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
659 Regs.push_back(HiLHS); in split64BitValueForMapping()
663 .addDef(HiLHS) in split64BitValueForMapping()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1530 SDValue LoLHS, HiLHS, LoRHS, HiRHS; in SplitVecRes_OverflowOp() local
1532 GetSplitVector(N->getOperand(0), LoLHS, HiLHS); in SplitVecRes_OverflowOp()
1535 std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_OverflowOp()
1543 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode(); in SplitVecRes_OverflowOp()
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| H A D | TargetLowering.cpp | 8443 SDValue HiLHS; in expandMULO() local
8449 HiLHS = in expandMULO()
8458 HiLHS = DAG.getConstant(0, dl, VT); in expandMULO()
8475 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; in expandMULO()
8478 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in expandMULO()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2957 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO() local
2959 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in LowerUMULO_SMULO()
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