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Searched refs:HalfVT (Results 1 – 13 of 13) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DValueTypes.h389 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
390 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
391 return HalfVT; in getHalfSizedIntegerVT()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1775 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerUDIVREM64() local
1777 SDValue One = DAG.getConstant(1, DL, HalfVT); in LowerUDIVREM64()
1778 SDValue Zero = DAG.getConstant(0, DL, HalfVT); in LowerUDIVREM64()
1782 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero); in LowerUDIVREM64()
1783 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One); in LowerUDIVREM64()
1786 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero); in LowerUDIVREM64()
1787 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One); in LowerUDIVREM64()
1792 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
1828 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2); in LowerUDIVREM64()
1829 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc); in LowerUDIVREM64()
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H A DSIISelLowering.cpp5572 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2); in lowerBUILD_VECTOR() local
5576 SDValue Lo = DAG.getBuildVector(HalfVT, SL, in lowerBUILD_VECTOR()
5578 SDValue Hi = DAG.getBuildVector(HalfVT, SL, in lowerBUILD_VECTOR()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp372 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4() local
390 createUnpackShuffleMask(HalfVT, MaskLowTemp, true, false); in interleave8bitStride4()
391 createUnpackShuffleMask(HalfVT, MaskHighTemp, false, false); in interleave8bitStride4()
H A DX86ISelLowering.cpp8654 EVT HalfVT = in EltsFromConsecutiveLoads() local
8657 EltsFromConsecutiveLoads(HalfVT, Elts.drop_back(HalfNumElems), DL, in EltsFromConsecutiveLoads()
9750 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in getHopForBuildVector() local
9753 SDValue Half = DAG.getNode(HOpcode, SDLoc(BV), HalfVT, V0, V1); in getHopForBuildVector()
10721 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerAVXCONCAT_VECTORS() local
10723 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerAVXCONCAT_VECTORS()
10725 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerAVXCONCAT_VECTORS()
10810 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerCONCAT_VECTORSvXi1() local
10812 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerCONCAT_VECTORSvXi1()
10814 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerCONCAT_VECTORSvXi1()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp1040 EVT HalfVT = in SplitInteger() local
1042 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
H A DLegalizeVectorTypes.cpp2835 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, in SplitVecOp_TruncateHelper() local
2842 HalfLo = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
2844 HalfHi = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
2851 HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); in SplitVecOp_TruncateHelper()
2852 HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); in SplitVecOp_TruncateHelper()
H A DDAGCombiner.cpp5154 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2); in visitANDLike() local
5160 TLI.isNarrowingProfitable(VT, HalfVT) && in visitANDLike()
5161 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) && in visitANDLike()
5162 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
5163 TLI.isTruncateFree(VT, HalfVT) && in visitANDLike()
5164 TLI.isZExtFree(HalfVT, VT)) { in visitANDLike()
5174 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout()); in visitANDLike()
5175 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT, in visitANDLike()
5178 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT); in visitANDLike()
5180 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK); in visitANDLike()
[all …]
H A DLegalizeIntegerTypes.cpp3955 EVT HalfVT = LHSLow.getValueType(); in ExpandIntRes_XMULO() local
3957 SDVTList VTHalfWithO = DAG.getVTList(HalfVT, BitVT); in ExpandIntRes_XMULO()
3959 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT); in ExpandIntRes_XMULO()
3970 SDValue HighSum = DAG.getNode(ISD::ADD, dl, HalfVT, One, Two); in ExpandIntRes_XMULO()
H A DTargetLowering.cpp1858 EVT HalfVT = Op.getOperand(0).getValueType(); in SimplifyDemandedBits() local
1859 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); in SimplifyDemandedBits()
8528 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in expandVecReduce() local
8529 if (!isOperationLegalOrCustom(BaseOpcode, HalfVT)) in expandVecReduce()
8534 Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi); in expandVecReduce()
8535 VT = HalfVT; in expandVecReduce()
H A DSelectionDAGBuilder.cpp196 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
200 PartVT, HalfVT, V); in getCopyFromParts()
202 RoundParts / 2, PartVT, HalfVT, V); in getCopyFromParts()
204 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
205 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp16362 MVT ExtVT, HalfVT; in PerformMinMaxCombine() local
16364 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
16367 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
16375 DAG.getNode(ARMISD::VQMOVNs, DL, HalfVT, DAG.getUNDEF(HalfVT), in PerformMinMaxCombine()
16402 MVT HalfVT; in PerformMinMaxCombine() local
16405 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
16408 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
16416 DAG.getNode(ARMISD::VQMOVNu, DL, HalfVT, DAG.getUNDEF(HalfVT), N0, in PerformMinMaxCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11114 auto *HalfVT = cast<FixedVectorType>(HalfV->getType()); in areExtractShuffleVectors() local
11115 return FullVT->getNumElements() == 2 * HalfVT->getNumElements(); in areExtractShuffleVectors()
14555 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in splitStores() local
14556 unsigned NumElts = HalfVT.getVectorNumElements(); in splitStores()
14557 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in splitStores()
14559 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in splitStores()
17495 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in LowerFixedLengthVectorIntDivideToSVE() local
17496 EVT FixedWidenedVT = HalfVT.widenIntegerVectorElementType(*DAG.getContext()); in LowerFixedLengthVectorIntDivideToSVE()