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Searched refs:GPRC (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td236 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRC:$rs1, opnd:$imm),
242 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, GPRC:$rs1, opnd:$imm),
287 def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
306 def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
325 def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
340 def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
359 def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
437 def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>,
439 def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>,
443 def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm),
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H A DRISCVInstrInfoB.td521 : RVInst16<(outs GPRC:$rs_wb), (ins GPRC:$rs), opcodestr, "$rs", [],
701 def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
702 (C_NOT GPRC:$rs1)>;
703 def : CompressPat<(SUB GPRC:$rs1, X0, GPRC:$rs1),
704 (C_NEG GPRC:$rs1)>;
708 def : CompressPat<(ADDUW GPRC:$rs1, GPRC:$rs1, X0),
709 (C_ZEXTW GPRC:$rs1)>;
H A DRISCVRegisterInfo.td73 // are not part of GPRC, the most restrictive register class used by the
165 def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp579 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
580 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
645 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in prepareDynamicAlloca() local
686 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
694 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
788 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
790 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
802 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
833 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore() local
835 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
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H A DPPCRegisterInfo.td285 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
290 let AltOrders = [(add (sub GPRC, R2), R2)];
310 def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
H A DPPCISelLowering.cpp11214 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in EmitPartwordAtomicBinary() local
11217 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11219 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11220 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11221 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11222 Register Mask2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11223 Register Mask3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11224 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11225 Register Tmp3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11226 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
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H A DPPCFrameLowering.cpp2274 const TargetRegisterClass &GPRC = PPC::GPRCRegClass; in addScavengingSpillSlot() local
2276 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
H A DPPCInstrVSX.td2661 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>;
2663 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>;
2665 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>;
2667 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>;
H A DPPCInstrInfo.td629 def gprc : RegisterOperand<GPRC> {
695 def spe4rc : RegisterOperand<GPRC> {
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DCodeGenerator.rst1090 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
1094 def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
1095 (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;