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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoA.td27 def GPRMemAtomic : RegisterOperand<GPR> {
39 (outs GPR:$rd), (ins GPRMemAtomic:$rs1),
54 (outs GPR:$rd), (ins GPRMemAtomic:$rs1, GPR:$rs2),
141 defm : AtomicStPat<atomic_store_8, SB, GPR>;
142 defm : AtomicStPat<atomic_store_16, SH, GPR>;
143 defm : AtomicStPat<atomic_store_32, SW, GPR>;
170 def : Pat<(atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr),
171 (AMOADD_W GPR:$addr, (SUB X0, GPR:$incr))>;
172 def : Pat<(atomic_load_sub_32_acquire GPR:$addr, GPR:$incr),
173 (AMOADD_W_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
[all …]
H A DRISCVInstrInfoB.td124 : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
132 : RVInstIShift<imm11_7, funct3, opcode, (outs GPR:$rd),
133 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
139 : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
140 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
147 : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
148 (ins GPR:$rs1, shfl_uimm:$shamt), opcodestr,
154 : RVInstR4<funct2, funct3, opcode, (outs GPR:$rd),
155 (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, argstr>;
161 : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt),
[all …]
H A DRISCVInstrInfo.td382 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
391 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
400 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
405 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
411 : RVInstIShift<imm11_7, funct3, OPC_OP_IMM, (outs GPR:$rd),
412 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
418 : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
424 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
430 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
436 : RVInstIShiftW<imm11_5, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
[all …]
H A DRISCVInstrInfoM.td75 def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
76 (MULW GPR:$rs1, GPR:$rs2)>;
85 def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
86 (assertzexti32 GPR:$rs2)), 0xffffffff),
87 (DIVU GPR:$rs1, GPR:$rs2)>;
88 def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
89 (assertzexti32 GPR:$rs2)), 0xffffffff),
90 (REMU GPR:$rs1, GPR:$rs2)>;
95 def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
96 (REMW GPR:$rs1, GPR:$rs2)>;
[all …]
H A DRISCVInstrInfoF.td95 : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
106 (ins GPR:$rs1, simm12:$imm12),
115 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12),
162 def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">,
166 def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>;
168 def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">,
172 def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;
174 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">,
183 def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
188 def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">,
[all …]
H A DRISCVInstrInfoD.td59 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
71 (ins GPR:$rs1, simm12:$imm12),
80 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
142 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
147 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">,
151 def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
153 def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">,
157 def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
159 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
164 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
[all …]
H A DRISCVInstrInfoVVLPatterns.td253 GPR:$vl, sew)>;
263 VMV0:$vm, GPR:$vl, sew)>;
286 GPR:$vl, sew)>;
296 VMV0:$vm, GPR:$vl, sew)>;
307 SplatPat, GPR>;
340 GPR:$vl, sew)>;
362 GPR:$vl, fvti.Log2SEW)>;
372 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
385 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
393 (SplatPat (XLenVT GPR:$rs2)), cc,
[all …]
H A DRISCVInstrInfoZfh.td61 : RVInstR<0b1010010, funct3, OPC_OP_FP, (outs GPR:$rd),
72 (ins GPR:$rs1, simm12:$imm12),
81 (ins FPR16:$rs2, GPR:$rs1, simm12:$imm12),
128 def FCVT_W_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.w.h">,
132 def : FPUnaryOpDynFrmAlias<FCVT_W_H, "fcvt.w.h", GPR, FPR16>;
134 def FCVT_WU_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.wu.h">,
138 def : FPUnaryOpDynFrmAlias<FCVT_WU_H, "fcvt.wu.h", GPR, FPR16>;
140 def FCVT_H_W : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.w">,
144 def : FPUnaryOpDynFrmAlias<FCVT_H_W, "fcvt.h.w", FPR16, GPR>;
146 def FCVT_H_WU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.wu">,
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/rs6000/
H A Dfusion.md238 (clobber (match_scratch:GPR 0 "=r"))]
245 [(set (match_dup 0) (sign_extend:GPR (match_dup 1)))
259 (clobber (match_scratch:GPR 0 "=r"))]
266 [(set (match_dup 0) (zero_extend:GPR (match_dup 1)))
322 (clobber (match_scratch:GPR 0 "=r"))]
329 [(set (match_dup 0) (zero_extend:GPR (match_dup 1)))
338 ;; load mode is QI result mode is GPR compare mode is CCUNS extend is zero
343 (set (match_operand:GPR 0 "gpc_reg_operand" "=r") (zero_extend:GPR (match_dup 1)))]
350 [(set (match_dup 0) (zero_extend:GPR (match_dup 1)))
362 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r")
[all …]
/netbsd-src/external/gpl3/gdb/dist/sim/mips/
H A Dmips3264r6.igen23 if (GPR[RS] == 0)
34 NIA = GPR[RT] + (EXTEND16(OFFSET) << 2);
42 if (GPR[RS] != 0)
54 NIA = GPR[RT] + EXTEND16(OFFSET);
67 if ((signed_word)GPR[RT] <= 0)
75 if ((signed_word)GPR[RT] >= 0)
83 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
100 if ((signed_word)GPR[RT] > 0)
108 if ((signed_word)GPR[RT] < 0)
116 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
[all …]
H A Dm16.igen38 GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
46 GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
56 GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
64 GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
74 GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
82 GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
92 GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
100 GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
110 GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
118 GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
[all …]
H A Dtx.igen12 + ((int64_t) EXTEND32 (GPR[RT])
13 * (int64_t) EXTEND32 (GPR[RS])));
15 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
20 GPR[RD] = LO;
30 + ((uint64_t) VL4_8 (GPR[RS])
31 * (uint64_t) VL4_8 (GPR[RT])));
33 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
38 GPR[RD] = LO;
/netbsd-src/external/gpl3/gcc/dist/gcc/config/mips/
H A Dsync.md61 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
62 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
64 (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
65 (match_operand:GPR 3 "arith_operand" "I,d")]
109 [(set (match_operand:GPR 0 "memory_operand" "+ZC,ZC")
110 (unspec_volatile:GPR
111 [(plus:GPR (match_dup 0)
112 (match_operand:GPR 1 "arith_operand" "I,d"))]
363 [(set (match_operand:GPR 0 "memory_operand" "+ZC")
364 (unspec_volatile:GPR
[all …]
H A Dmips.md793 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
795 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
797 ;; A copy of GPR that can be used when a pattern has two independent
879 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
902 ;; Mode attributes for GPR loads.
1217 [(match_operand:GPR 1 "reg_or_0_operand")
1218 (match_operand:GPR 2 "arith_operand")])
1227 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1228 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1229 (match_operand:GPR 2 "reg_or_0_operand" "dJ")])
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/mips/
H A Dsync.md61 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
62 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
64 (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
65 (match_operand:GPR 3 "arith_operand" "I,d")]
109 [(set (match_operand:GPR 0 "memory_operand" "+ZC,ZC")
110 (unspec_volatile:GPR
111 [(plus:GPR (match_dup 0)
112 (match_operand:GPR 1 "arith_operand" "I,d"))]
363 [(set (match_operand:GPR 0 "memory_operand" "+ZC")
364 (unspec_volatile:GPR
[all …]
H A Dmips.md793 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
795 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
797 ;; A copy of GPR that can be used when a pattern has two independent
879 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
902 ;; Mode attributes for GPR loads.
1217 [(match_operand:GPR 1 "reg_or_0_operand")
1218 (match_operand:GPR 2 "arith_operand")])
1227 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1228 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1229 (match_operand:GPR 2 "reg_or_0_operand" "dJ")])
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td192 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
204 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
226 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/loongarch/
H A Dsync.md75 [(set (match_operand:GPR 0 "memory_operand" "+ZB")
76 (unspec_volatile:GPR
77 [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
85 [(set (match_operand:GPR 0 "memory_operand" "+ZB")
86 (unspec_volatile:GPR
87 [(any_atomic:GPR (match_dup 0)
88 (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
96 [(set (match_operand:GPR 0 "register_operand" "=&r")
97 (match_operand:GPR 1 "memory_operand" "+ZB"))
99 (unspec_volatile:GPR
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrInfo.td389 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
764 let MIOperandInfo = (ops GPR, i32imm);
775 let MIOperandInfo = (ops GPR, GPR, i32imm);
786 let MIOperandInfo = (ops GPR, i32imm);
1094 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
1115 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1171 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1172 // the GPR is purely vestigal at this point.
1193 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1218 let MIOperandInfo = (ops GPR, i32imm);
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/riscv/
H A Dsync.md62 [(set (match_operand:GPR 0 "memory_operand" "=A")
63 (unspec_volatile:GPR
64 [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
72 [(set (match_operand:GPR 0 "memory_operand" "+A")
73 (unspec_volatile:GPR
74 [(any_atomic:GPR (match_dup 0)
75 (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
83 [(set (match_operand:GPR 0 "register_operand" "=&r")
84 (match_operand:GPR 1 "memory_operand" "+A"))
86 (unspec_volatile:GPR
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td80 let MIOperandInfo = (ops GPR, i16imm);
160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
267 (outs GPR:$dst),
268 (ins GPR:$src2, GPR:$src),
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
272 (outs GPR:$dst),
273 (ins GPR:$src2, i64imm:$imm),
275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
313 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/riscv/
H A Dsync.md62 [(set (match_operand:GPR 0 "memory_operand" "=A")
63 (unspec_volatile:GPR
64 [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
72 [(set (match_operand:GPR 0 "memory_operand" "+A")
73 (unspec_volatile:GPR
74 [(any_atomic:GPR (match_dup 0)
75 (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
83 [(set (match_operand:GPR 0 "register_operand" "=&r")
84 (match_operand:GPR 1 "memory_operand" "+A"))
86 (unspec_volatile:GPR
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td157 [(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;
162 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
163 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
165 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
166 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
168 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
169 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
171 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
172 [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
191 def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),
[all …]
H A DCSKYInstrFormats.td76 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
89 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
91 [(set GPR:$rz, ImmType:$imm16)]> {
105 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), ins,
127 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
140 (ins GPR:$rx, operand:$imm2),
179 (ins GPR:$rx, operand:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
191 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
205 : CSKY32Inst<AddrModeNone, 0x39, (outs GPR:$rz),
206 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/s390/
H A Ds390.md649 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
651 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
767 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
797 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
801 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
814 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
818 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
958 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
959 (match_operand:GPR 1 "const0_operand" "")))
960 (set (match_operand:GPR 2 "register_operand" "=d,d")
[all …]

12345678910>>...16