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Searched refs:FirstReg (Results 1 – 12 of 12) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp392 Register FirstReg; in CreateRegs() local
400 if (!FirstReg) FirstReg = R; in CreateRegs()
403 return FirstReg; in CreateRegs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp497 unsigned FirstReg = 0; in ScanInstruction() local
504 if (FirstReg != 0) { in ScanInstruction()
506 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
509 FirstReg = Reg; in ScanInstruction()
513 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3365 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3370 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3382 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3400 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3423 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr), in expandLoadSingleImmToFPR()
3436 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3443 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, in expandLoadDoubleImmToGPR()
3447 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3451 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3485 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp2258 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord() argument
2317 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2319 if (FirstReg == SecondReg) in CanFormLdStDWord()
2421 Register FirstReg, SecondReg; in RescheduleOps() local
2429 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2436 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2442 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2456 .addReg(FirstReg) in RescheduleOps()
2474 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2475 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1296 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1297 Reg = FirstReg; in printVectorList()
1298 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1299 Reg = FirstReg; in printVectorList()
1300 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1301 Reg = FirstReg; in printVectorList()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4319 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs() argument
4324 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4333 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
4356 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
4372 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg() argument
4382 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4396 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4445 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4519 unsigned FirstReg = 0; in HandleByVal() local
4535 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
[all …]
H A DMipsISelLowering.h567 const Argument *FuncArg, unsigned FirstReg,
576 unsigned FirstReg, unsigned LastReg,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1570 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
1571 Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() - in addVectorListOperands()
3501 unsigned FirstReg; in tryParseVectorList() local
3502 auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch); in tryParseVectorList()
3512 int64_t PrevReg = FirstReg; in tryParseVectorList()
3582 FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(), in tryParseVectorList()
6157 unsigned FirstReg; in tryParseGPRSeqPair() local
6158 OperandMatchResultTy Res = tryParseScalarRegister(FirstReg); in tryParseGPRSeqPair()
6167 bool isXReg = XRegClass.contains(FirstReg), in tryParseGPRSeqPair()
6168 isWReg = WRegClass.contains(FirstReg); in tryParseGPRSeqPair()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1632 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
1638 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
1639 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
1641 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
1643 Register OldFirstReg = FirstReg; in insertSelect()
1644 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
1645 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
1650 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
H A DPPCISelLowering.cpp6710 const unsigned FirstReg = State.AllocateReg(PPC::R9); in CC_AIX() local
6712 assert(FirstReg && SecondReg && in CC_AIX()
6715 CCValAssign::getCustomReg(ValNo, ValVT, FirstReg, RegVT, LocInfo)); in CC_AIX()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp2265 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
2273 FirstReg = Count - 1; in computeCalleeSaveRegisterPairs()
2279 for (unsigned i = FirstReg; i < Count; i += RegInc) { in computeCalleeSaveRegisterPairs()
2299 bool IsFirst = i == FirstReg; in computeCalleeSaveRegisterPairs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4754 unsigned FirstReg = Reg; in parseVectorList() local
4763 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
4917 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
4921 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); in parseVectorList()
4925 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()