Searched refs:FinalReg (Results 1 – 3 of 3) sorted by relevance
806 FinalReg = InProlog ? X86::RDX in emitStackProbeInlineWindowsCoreCLR64() local867 BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg) in emitStackProbeInlineWindowsCoreCLR64()885 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg); in emitStackProbeInlineWindowsCoreCLR64()890 RoundMBB->addLiveIn(FinalReg); in emitStackProbeInlineWindowsCoreCLR64()892 .addReg(FinalReg) in emitStackProbeInlineWindowsCoreCLR64()
1664 unsigned FinalReg = FinalOp.Mem.BaseReg; in VerifyAndAdjustOperands() local1685 bool IsSI = IsSIReg(FinalReg); in VerifyAndAdjustOperands()1686 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()1688 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()1698 FinalOp.Mem.BaseReg = FinalReg; in VerifyAndAdjustOperands()
1203 unsigned FinalReg = SubReg; in buildSpillLoadStore() local1254 FinalReg) in buildSpillLoadStore()