Searched refs:FeatureBits (Results 1 – 10 of 10) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 210 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures); in InitMCProcessorInfo() 221 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures); in setDefaultFeatures() 241 FeatureBits.flip(FB); in ToggleFeature() 242 return FeatureBits; in ToggleFeature() 246 FeatureBits ^= FB; in ToggleFeature() 247 return FeatureBits; in ToggleFeature() 252 SetImpliedBits(FeatureBits, FB, ProcFeatures); in SetFeatureBitsTransitively() 253 return FeatureBits; in SetFeatureBitsTransitively() 260 FeatureBits.reset(I); in ClearFeatureBitsTransitively() 261 ClearImpliedBits(FeatureBits, I, ProcFeatures); in ClearFeatureBitsTransitively() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.cpp | 26 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, in computeTargetABI() argument 30 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in computeTargetABI() 90 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { in validate() argument 91 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) in validate() 93 if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit]) in validate() 95 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) in validate()
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| H A D | RISCVBaseInfo.h | 290 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, 307 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 91 FeatureBitset FeatureBits; // Feature bits for current CPU + FS variable 111 const FeatureBitset& getFeatureBits() const { return FeatureBits; } in getFeatureBits() 113 FeatureBits = FeatureBits_; in setFeatureBits() 119 return FeatureBits[Feature]; in hasFeature()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 64 const FeatureBitset &FeatureBits = in DecodeGPRRegisterClass() local 68 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in DecodeGPRRegisterClass()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 867 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local 868 if (FeatureBits[ARM::FeatureMClass]) { in printMSRMaskOperand() 874 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { in printMSRMaskOperand() 884 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 765 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); in AddThumbPredicate() local 792 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate() 2333 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeHINTInstruction() local 2344 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction() 2546 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeSETPANInstruction() local 2548 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction() 2549 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction() 4537 const FeatureBitset &FeatureBits = in DecodeThumbTableBranch() local 4544 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; in DecodeThumbTableBranch() 4680 const FeatureBitset &FeatureBits = in DecodeMSRMask() local [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 206 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); in popFeatureBits() local 207 copySTI().setFeatureBits(FeatureBits); in popFeatureBits() 208 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); in popFeatureBits()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 474 FeatureBitset FeatureBits = STI.getFeatureBits(); in selectArch() local 475 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; in selectArch() 476 STI.setFeatureBits(FeatureBits); in selectArch()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 5167 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits(); in getMClassRegisterMask() local 5168 if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits)) in getMClassRegisterMask()
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