| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 95 DAG_FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 860 FSIN, enumerator
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| H A D | BasicTTIImpl.h | 1529 ISDs.push_back(ISD::FSIN); in getTypeBasedIntrinsicInstrCost()
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| /netbsd-src/sys/arch/m68k/m68k/ |
| H A D | db_disasm.h | 371 #define FSIN ENCFT(0,0,1,1,1,0) macro
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| H A D | db_disasm.c | 1468 case FSIN: in opcode_fpu()
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| /netbsd-src/sys/arch/m68k/fpe/ |
| H A D | README | 71 FCOSH, FSINH, FTANH, FCOS, FSIN, FTAN, FSINCOS,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 117 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
460 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
752 case ISD::FSIN: in LowerTrig()
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| H A D | AMDGPUISelLowering.cpp | 482 setOperationAction(ISD::FSIN, VT, Expand); in AMDGPUTargetLowering()
595 case ISD::FSIN: in fnegFoldsIntoOp()
3799 case ISD::FSIN: in performFNegCombine()
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| H A D | SIISelLowering.cpp | 486 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
549 setOperationAction(ISD::FSIN, MVT::f16, Custom); in SITargetLowering()
4488 case ISD::FSIN: in LowerOperation()
8727 case ISD::FSIN: in LowerTrig()
9365 case ISD::FSIN: in fp16SrcZerosHighBits()
9562 case ISD::FSIN: in isCanonicalized()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 198 case ISD::FSIN: return "fsin"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 119 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1234 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2241 case ISD::FSIN: in PromoteFloatResult()
2606 case ISD::FSIN: in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 2209 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2210 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3154 case ISD::FSIN: in ExpandNode()
3961 case ISD::FSIN: in ConvertNodeToLibcall()
4736 case ISD::FSIN: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 416 case ISD::FSIN: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 99 case ISD::FSIN: in ScalarizeVectorResult()
993 case ISD::FSIN: in SplitVectorResult()
3119 case ISD::FSIN: in WidenVectorResult()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 892 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 747 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1625 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1630 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1635 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 352 setOperationAction(ISD::FSIN, VT, Expand); in AArch64TargetLowering()
428 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
560 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
561 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
585 setOperationAction(ISD::FSIN, MVT::f16, Promote); in AArch64TargetLowering()
586 setOperationAction(ISD::FSIN, MVT::v4f16, Expand); in AArch64TargetLowering()
587 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); in AArch64TargetLowering()
972 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); in AArch64TargetLowering()
1364 setOperationAction(ISD::FSIN, VT, Expand); in addTypeForNEON()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1593 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1638 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 109 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 366 setOperationAction(ISD::FSIN, VT, Expand); in addMVEVectorTypes()
841 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
862 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
878 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
1021 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1384 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1385 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
1468 setOperationAction(ISD::FSIN, MVT::f16, Promote); in ARMTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 433 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
434 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 243 setOperationAction(ISD::FSIN, VT, Expand); in initSPUActions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 478 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 365 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
370 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
800 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
1128 setOperationAction(ISD::FSIN, MVT::f128, Expand); in PPCTargetLowering()
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