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Searched refs:FSEL (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/usr.bin/xlint/lint1/
H A Dop.h116 FSEL, enumerator
H A Dtree.c608 if (op == INDIR || op == FSEL) { in check_nonportable_char_comparison()
1313 op_t nop = rn->tn_type->t_bitfield ? FSEL : INDIR; in build_colon()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DREADME.txt548 ; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
H A DPPCISelLowering.h52 FSEL, enumerator
H A DPPCISelLowering.cpp1569 case PPCISD::FSEL: return "PPCISD::FSEL"; in getTargetNodeName()
7849 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7852 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7862 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7871 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7885 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7888 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7895 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
7901 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7907 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
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H A DP9InstrResources.td455 (instregex "FSEL(D|S)_rec$")
H A DPPCInstrInfo.td197 def PPCfsel : SDNode<"PPCISD::FSEL",
3258 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/rs6000/
H A Drs6000.md5108 ;; even when we don't have the appropriate max/min instruction using the FSEL
/netbsd-src/external/gpl3/gcc/dist/gcc/config/rs6000/
H A Drs6000.md5390 ;; even when we don't have the appropriate max/min instruction using the FSEL
/netbsd-src/external/gpl3/gcc/dist/gcc/
H A DChangeLog-201622772 (fselsfsf4): Combine FSEL cases into a single insn, using SFDF and
22789 FSEL, ISA 2.06 min/max, and ISA 3.0 min/max instrucitons.