Home
last modified time | relevance | path

Searched refs:FRINT (Results 1 – 25 of 50) sorted by relevance

12

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DConstrainedOps.def92 DAG_FUNCTION(rint, 1, 1, experimental_constrained_rint, FRINT)
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h871 FRINT, enumerator
H A DBasicTTIImpl.h1583 ISDs.push_back(ISD::FRINT); in getTypeBasedIntrinsicInstrCost()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedA57.td508 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
510 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
582 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
H A DAArch64SchedTSV110.td480 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT.+r")>;
670 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedFalkorDetails.td592 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
617 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>;
1123 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>;
H A DAArch64SchedExynosM3.td542 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
657 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedExynosM5.td712 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>;
836 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedExynosM4.td653 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>;
798 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedThunderX2T99.td1185 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1406 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1409 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
H A DAArch64SchedThunderX3T110.td1293 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1514 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1517 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
H A DAArch64SchedKryoDetails.td963 (instregex "FRINT(A|I|M|N|P|X|Z)(S|D)r")>;
969 (instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>;
975 (instregex "FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)")>;
H A DAArch64SchedCyclone.td576 // FRINT(AIMNPXZ) V,V
H A DAArch64ISelLowering.cpp427 setOperationAction(ISD::FRINT, MVT::f128, Expand); in AArch64TargetLowering()
623 setOperationAction(ISD::FRINT, MVT::f16, Promote); in AArch64TargetLowering()
655 setOperationAction(ISD::FRINT, MVT::v4f16, Expand); in AArch64TargetLowering()
671 setOperationAction(ISD::FRINT, MVT::v8f16, Expand); in AArch64TargetLowering()
687 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
705 setOperationAction(ISD::FRINT, MVT::f16, Legal); in AArch64TargetLowering()
971 setOperationAction(ISD::FRINT, MVT::v1f64, Expand); in AArch64TargetLowering()
1098 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
1109 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
1236 setOperationAction(ISD::FRINT, VT, Custom); in AArch64TargetLowering()
[all …]
H A DAArch64SchedA64FX.td1561 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1800 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1803 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp499 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
608 Opcode = ISD::FRINT; break; in mightUseCTR()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp209 case ISD::FRINT: return "frint"; in getOperationName()
H A DLegalizeFloatTypes.cpp113 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
1228 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
2238 case ISD::FRINT: in PromoteFloatResult()
2603 case ISD::FRINT: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp427 case ISD::FRINT: in LegalizeOp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp299 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
479 setOperationAction(ISD::FRINT, VT, Expand); in AMDGPUTargetLowering()
597 case ISD::FRINT: in fnegFoldsIntoOp()
1247 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
2232 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
3797 case ISD::FRINT: in performFNegCombine()
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/
H A Dthunderx3t110.md428 ; FRINT*: latency 5 throughput 1/4
/netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/
H A Dthunderx3t110.md428 ; FRINT*: latency 5 throughput 1/4
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp114 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
211 ISD::FEXP, ISD::FEXP2, ISD::FRINT}) in WebAssemblyTargetLowering()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp148 setOperationAction(ISD::FRINT, MVT::f16, Promote); in MipsSETargetLowering()
394 setOperationAction(ISD::FRINT, Ty, Legal); in addMSAFloatType()
1917 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp871 setOperationAction(ISD::FRINT, VT, Expand); in initActions()

12