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/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dnds32-asm.c526 {"flsi", "=fst,[%ra{+%i12s2}]", OP6 (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
527 {"flsi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
529 {"fssi", "=fst,[%ra{+%i12s2}]", OP6 (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
530 {"fssi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
532 {"fldi", "=fdt,[%ra{+%i12s2}]", OP6 (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
533 {"fldi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
535 {"fsdi", "=fdt,[%ra{+%i12s2}]", OP6 (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
536 {"fsdi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
539 {"fadds", "=fst,%fsa,%fsb", FS1 (FADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
540 {"fsubs", "=fst,%fsa,%fsb", FS1 (FSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dnds32-asm.c526 {"flsi", "=fst,[%ra{+%i12s2}]", OP6 (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
527 {"flsi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
529 {"fssi", "=fst,[%ra{+%i12s2}]", OP6 (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
530 {"fssi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
532 {"fldi", "=fdt,[%ra{+%i12s2}]", OP6 (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
533 {"fldi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
535 {"fsdi", "=fdt,[%ra{+%i12s2}]", OP6 (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
536 {"fsdi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
539 {"fadds", "=fst,%fsa,%fsb", FS1 (FADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
540 {"fsubs", "=fst,%fsa,%fsb", FS1 (FSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/lib/Basic/Targets/
H A DAArch64.cpp263 if (FPU & NeonMode) { in getTargetDefines()
269 if (FPU & SveMode) in getTargetDefines()
314 if ((FPU & NeonMode) && HasFullFP16) in getTargetDefines()
341 if ((FPU & SveMode) && HasBFloat16) { in getTargetDefines()
345 if ((FPU & SveMode) && HasMatmulFP64) in getTargetDefines()
348 if ((FPU & SveMode) && HasMatmulFP32) in getTargetDefines()
351 if ((FPU & SveMode) && HasMatMul) in getTargetDefines()
354 if ((FPU & NeonMode) && HasFP16FML) in getTargetDefines()
429 (Feature == "neon" && (FPU & NeonMode)) || in hasFeature()
434 (FPU & SveMode)); in hasFeature()
[all …]
H A DARM.cpp427 FPU = 0; in handleTargetFeatures()
450 FPU |= VFP2FPU; in handleTargetFeatures()
456 FPU |= VFP3FPU; in handleTargetFeatures()
462 FPU |= VFP4FPU; in handleTargetFeatures()
468 FPU |= FPARMV8; in handleTargetFeatures()
473 FPU |= NeonFPU; in handleTargetFeatures()
508 FPU |= FPARMV8; in handleTargetFeatures()
541 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { in handleTargetFeatures()
560 .Case("neon", (FPU & NeonFPU) && !SoftFloat) in hasFeature()
561 .Case("vfp", FPU && !SoftFloat) in hasFeature()
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/sh/
H A Dsh.opt24 ;; Set if the default precision of the FPU is single.
27 ;; Set if the a double-precision FPU is present but is restricted to
50 Generate default double-precision SH2a-FPU code.
54 Generate SH2a FPU-less code.
58 Generate default single-precision SH2a-FPU code.
62 Generate only single-precision SH2a-FPU code.
96 Generate SH4 FPU-less code.
100 Generate SH4-100 FPU-less code.
104 Generate SH4-200 FPU-less code.
108 Generate SH4-300 FPU-less code.
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/sh/
H A Dsh.opt24 ;; Set if the default precision of the FPU is single.
27 ;; Set if the a double-precision FPU is present but is restricted to
50 Generate default double-precision SH2a-FPU code.
54 Generate SH2a FPU-less code.
58 Generate default single-precision SH2a-FPU code.
62 Generate only single-precision SH2a-FPU code.
96 Generate SH4 FPU-less code.
100 Generate SH4-100 FPU-less code.
104 Generate SH4-200 FPU-less code.
108 Generate SH4-300 FPU-less code.
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arc/
H A DarcHS4x.md95 ;; FPU unit
102 ;; FPU FUSE unit
109 ;; FPU SP SQRT/DIV unit
116 ;; FPU DP SQRT/DIV unit
123 ;; FPU CVT unit
183 ;;BYPASS FPU ->
191 ;;BYPASS FPU FUSE ->
199 ;;BYPASS FPU SP DIV ->
207 ;;BYPASS FPU DP DIV ->
215 ;;BYPASS FPU CVT ->
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arc/
H A DarcHS4x.md95 ;; FPU unit
102 ;; FPU FUSE unit
109 ;; FPU SP SQRT/DIV unit
116 ;; FPU DP SQRT/DIV unit
123 ;; FPU CVT unit
183 ;;BYPASS FPU ->
191 ;;BYPASS FPU FUSE ->
199 ;;BYPASS FPU SP DIV ->
207 ;;BYPASS FPU DP DIV ->
215 ;;BYPASS FPU CVT ->
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ196.td83 def : WriteRes<FPU, [Z196_FPUnit]>;
88 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
718 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
719 def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
744 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
748 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
749 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
754 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
756 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
757 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
[all …]
H A DSystemZScheduleZEC12.td84 def : WriteRes<FPU, [ZEC12_FPUnit]>;
89 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
756 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
757 def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
782 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
786 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
787 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
792 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
794 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
795 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
[all …]
/netbsd-src/sys/arch/playstation2/conf/
H A Dstd.playstation212 options NOFPU # Don't use FPU (R5900 FPU is single float only)
13 options FPEMUL # emulate FPU insn
/netbsd-src/external/cddl/dtracetoolkit/dist/Examples/
H A Dcputypes_example.txt7 CPU CHIP PSET LGRP CLOCK TYPE FPU
17 CPU CHIP PSET LGRP CLOCK TYPE FPU
33 CPU CHIP PSET LGRP CLOCK TYPE FPU
/netbsd-src/external/cddl/dtracetoolkit/dist/Docs/Examples/
H A Dcputypes_example.txt7 CPU CHIP PSET LGRP CLOCK TYPE FPU
17 CPU CHIP PSET LGRP CLOCK TYPE FPU
33 CPU CHIP PSET LGRP CLOCK TYPE FPU
/netbsd-src/external/gpl3/gcc/dist/gcc/config/visium/
H A Dvisium.opt32 Target Mask(FPU)
36 Target RejectNegative Mask(FPU) MaskExists
40 Target RejectNegative InverseMask(FPU)
82 ; Generate code for an IEEE-compliant FPU
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/visium/
H A Dvisium.opt32 Target Report Mask(FPU)
36 Target RejectNegative Mask(FPU) MaskExists
40 Target RejectNegative InverseMask(FPU)
82 ; Generate code for an IEEE-compliant FPU
/netbsd-src/external/gpl3/gdb/dist/sim/erc32/
H A DREADME.sis22 The '-nfp' will disable the simulated FPU, so each FPU instruction will
23 generate a FPU disabled trap. The '-freq' switch can be used to define
75 Prints the FPU registers
150 FPU from Matra MHS. These are roughly equivalent to the Cypress C601
152 maintained and inremented according the IU and FPU instruction timing.
153 The parallel execution between the IU and FPU is modelled, as well as
154 stalls due to operand dependencies (FPU). The core interacts with the
305 7. IU and FPU instruction timing.
340 The parallel operation between the IU and FPU is modelled. This means
341 that a FPU instruction will execute in parallel with other instructions as
[all …]
/netbsd-src/sys/arch/evbmips/conf/
H A Dstd.rasoc10 options NOFPU # No FPU
11 options FPEMUL # emulate FPU insn
/netbsd-src/sys/arch/hpcmips/conf/
H A Dstd.hpcmips8 options NOFPU # No FPU
9 options FPEMUL # emulate FPU insn
H A Dstd.lcard8 options NOFPU # No FPU
9 options FPEMUL # emulate FPU insn
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/rs6000/
H A D6xx.md27 ;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
28 ;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
31 ;; FPU 3 stage pipelined
39 ;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
156 ; FPU PPC604{,e},PPC620
H A Dtitan.md126 ;; === FPU scheduling ===
128 ;; In order to keep the automaton for the Titan FPU efficient and
135 ;; * the FPU runs at half the core frequency
137 ;; * the FPU has a shared result bus for all its units
/netbsd-src/external/gpl3/gcc/dist/gcc/config/rs6000/
H A D6xx.md27 ;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
28 ;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
31 ;; FPU 3 stage pipelined
39 ;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
156 ; FPU PPC604{,e},PPC620
H A Dtitan.md126 ;; === FPU scheduling ===
128 ;; In order to keep the automaton for the Titan FPU efficient and
135 ;; * the FPU runs at half the core frequency
137 ;; * the FPU has a shared result bus for all its units
/netbsd-src/sys/arch/sparc64/sparc64/
H A Dmp_subr.S364 btst FPRS_DL|FPRS_DU, %g5 ! Both FPU halves clean?
373 btst FPRS_DL, %g5 ! Lower FPU clean?
374 bz,a,pt %icc, 1f ! Then skip it, but upper FPU not clean
381 btst FPRS_DU, %g5 ! Upper FPU clean?
395 wr %g0, FPRS_FEF, %fprs ! Mark FPU clean
/netbsd-src/sys/arch/m68k/m68k/
H A Dswitch_subr.s51 * If your port uses one or more non-motorola FPU devices, you must use:
56 * two assembly sub-routines for saving and restoring FPU context:
104 tstl _C_LABEL(fputype) | Do we have an FPU?
175 tstl _C_LABEL(fputype) | Do we have an FPU?
227 tstl _C_LABEL(fputype) | Do we have FPU?
264 * On machines with an FPU, generate an "idle" state frame to be
267 * Before calling, make sure the machine actually has an FPU ...
273 frestore (%sp) | Effectively `resets' the FPU
276 /* Loading '0.0' will change FPU to "idle". */
285 /* Reset the FPU agai
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