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Searched refs:FP64 (Results 1 – 25 of 34) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td23 def LTDR : UnaryRR <"ltdr", 0x22, null_frag, FP64, FP64>;
32 def LEDR : UnaryRR <"ledr", 0x35, null_frag, FP32, FP64>;
34 def LDXR : UnaryRR <"ldxr", 0x25, null_frag, FP64, FP128>;
36 def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>;
37 def LRDR : UnaryRR <"lrdr", 0x25, null_frag, FP64, FP128>;
41 def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64, FP32>;
43 def LXDR : UnaryRRE<"lxdr", 0xB325, null_frag, FP128, FP64>;
45 def LDE : UnaryRXE<"lde", 0xED24, null_frag, FP64, 4>;
51 def CDFR : UnaryRRE<"cdfr", 0xB3B5, null_frag, FP64, GR32>;
55 def CDGR : UnaryRRE<"cdgr", 0xB3C5, null_frag, FP64, GR64>;
[all …]
H A DSystemZInstrDFP.td23 def LTDTR : UnaryRRE<"ltdtr", 0xB3D6, null_frag, FP64, FP64>;
35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
41 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
42 def LXDTR : BinaryRRFd<"lxdtr", 0xB3DC, FP128, FP64>;
47 def CDGTR : UnaryRRE<"cdgtr", 0xB3F1, null_frag, FP64, GR64>;
50 def CDGTRA : TernaryRRFe<"cdgtra", 0xB3F1, FP64, GR64>;
52 def CDFTR : TernaryRRFe<"cdftr", 0xB951, FP64, GR32>;
59 def CDLGTR : TernaryRRFe<"cdlgtr", 0xB952, FP64, GR64>;
61 def CDLFTR : TernaryRRFe<"cdlftr", 0xB953, FP64, GR32>;
67 def CGDTR : BinaryRRFe<"cgdtr", 0xB3E1, GR64, FP64>;
[all …]
H A DSystemZInstrFP.td22 def SelectF64 : SelectWrapper<f64, FP64>;
30 defm CondStoreF64 : CondStores<FP64, simple_store,
40 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>;
46 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
58 defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>;
66 defm : CompareZeroFP<LTDBRCompare, FP64>;
75 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
80 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>;
86 def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
87 def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
[all …]
H A DSystemZRegisterInfo.td244 defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;
H A DSystemZInstrVector.td1620 defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_h64>;
1626 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0),
1627 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1629 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1),
1630 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
/netbsd-src/external/apache2/llvm/dist/clang/lib/Basic/Targets/
H A DMips.cpp143 case FP64: in getTargetDefines()
148 if (FPMode == FP64 || IsSingleFloat) in getTargetDefines()
217 .Case("fp64", FPMode == FP64) in hasFeature()
279 if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat && in validateTarget()
285 if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" || in validateTarget()
291 if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" || in validateTarget()
H A DMips.h59 enum FPModeEnum { FPXX, FP32, FP64 } FPMode; enumerator
316 FPMode = isFP64Default() ? FP64 : FPXX; in handleTargetFeatures()
336 FPMode = FP64; in handleTargetFeatures()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.td31 def FP64 : WebAssemblyReg<"%FP64">;
63 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
H A DWebAssemblyRegisterInfo.cpp48 WebAssembly::FP64}) in getReservedRegs()
147 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}}; in getFrameRegister()
H A DWebAssemblyFrameLowering.cpp134 ? WebAssembly::FP64 in getFPReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.h119 bool FP64) const;
122 bool FP64) const;
H A DMipsSEFrameLowering.cpp85 MachineBasicBlock::iterator I, bool FP64) const;
87 MachineBasicBlock::iterator I, bool FP64) const;
288 bool FP64) const { in expandBuildPairF64()
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
344 bool FP64) const { in expandExtractElementF64()
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
H A DMipsSEInstrInfo.cpp784 bool FP64) const { in expandExtractElementF64()
816 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) in expandExtractElementF64()
817 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), in expandExtractElementF64()
826 bool isMicroMips, bool FP64) const { in expandBuildPairF64()
872 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) in expandBuildPairF64()
873 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), in expandBuildPairF64()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DGCNSubtarget.h104 bool FP64; variable
293 return FP64; in hasFP64()
301 return FP64; in hasHWFP64()
H A DAMDGPUFeatures.td10 "FP64",
H A DR600Subtarget.h46 bool FP64; variable
H A DAMDGPUSubtarget.cpp233 FP64(false), in GCNSubtarget()
632 FP64(false), in R600Subtarget()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64.td402 "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td2515 // SVE ACLE: 7.4/5. FP64/FP32 matrix multiply extensions
/netbsd-src/external/gpl3/binutils/dist/gold/
H A DChangeLog-2016875 compare FP64 state.
/netbsd-src/external/gpl3/binutils.old/dist/gold/
H A DChangeLog-2016875 compare FP64 state.
/netbsd-src/external/gpl3/gcc.old/dist/
H A DNEWS5915 and FP64. The meaning of the -mfp64 command-line option has
5916 changed. It is now used to enable the FP64A and FP64 ABI
5932 + The o32 FP64 extension also requires that floating-point
5934 registers. Code that adheres to the o32 FP64 variant is
/netbsd-src/external/gpl3/gcc/dist/gcc/doc/
H A Dinstall.texi1506 Use the o32 FP64 ABI extension, as with the @option{-mfp64} command-line
H A Dgccinstall.info1276 Use the o32 FP64 ABI extension, as with the '-mfp64'
/netbsd-src/external/gpl3/gcc.old/dist/gcc/doc/
H A Dinstall.texi1390 Use the o32 FP64 ABI extension, as with the @option{-mfp64} command-line

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