Searched refs:FMAD (Results 1 – 18 of 18) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 464 FMAD, enumerator
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| H A D | TargetLowering.h | 2718 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegal()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCodeGenPrepare.cpp | 918 auto FMAD = !ST->hasMadMacF32Insts() in expandDivRem24Impl() local
921 Value *FR = Builder.CreateIntrinsic(FMAD, in expandDivRem24Impl()
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| H A D | AMDGPUISelLowering.cpp | 590 case ISD::FMAD: in fnegFoldsIntoOp()
821 case ISD::FMAD: { in getNegatedExpression()
1724 (unsigned)ISD::FMAD : in LowerDIVREM24()
1808 unsigned FMAD = !Subtarget->hasMadMacF32Insts() ? in LowerUDIVREM64() local
1811 (unsigned)ISD::FMAD : in LowerUDIVREM64()
1816 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
1825 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
3717 case ISD::FMAD: { in performFNegCombine()
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| H A D | SIISelLowering.cpp | 414 setOperationAction(ISD::FMAD, MVT::f32, Legal); in SITargetLowering()
569 setOperationAction(ISD::FMAD, MVT::f16, Legal); in SITargetLowering()
868 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) || in isFPExtFoldable()
9356 case ISD::FMAD: in fp16SrcZerosHighBits()
9530 case ISD::FMAD: in isCanonicalized()
10283 isOperationLegal(ISD::FMAD, VT)) in getFusedOpcode()
10284 return ISD::FMAD; in getFusedOpcode()
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| H A D | R600ISelLowering.cpp | 203 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
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| H A D | AMDGPUISelDAGToDAG.cpp | 871 case ISD::FMAD: in Select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 262 case ISD::FMAD: return "fmad"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 2259 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
2624 case ISD::FMAD: R = SoftPromoteHalfRes_FMAD(N); break; in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 3170 case ISD::FMAD: in ExpandNode()
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| H A D | DAGCombiner.cpp | 12851 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
13060 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
13364 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMADistributiveCombine()
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| H A D | TargetLowering.cpp | 6182 case ISD::FMAD: { in getNegatedExpression()
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| H A D | SelectionDAG.cpp | 4327 case ISD::FMAD: { in isKnownNeverNaN()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 748 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 460 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>;
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/ |
| H A D | aarch64-sve.md | 6856 ;; - FMAD
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/ |
| H A D | aarch64-sve.md | 6981 ;; - FMAD
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 40802 case ISD::FMAD: in scalarizeExtEltFP()
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