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Searched refs:ExtraVT (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp572 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); in LegalizeStoreOps() local
591 ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo); in LegalizeStoreOps()
610 ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo); in LegalizeStoreOps()
783 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); in LegalizeLoadOps() local
800 ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo); in LegalizeLoadOps()
828 ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo); in LegalizeLoadOps()
2888 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); in ExpandNode() local
2898 if (ExtraVT.getSizeInBits() == 1) { in ExpandNode()
2911 ExtraVT.getScalarSizeInBits(); in ExpandNode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2749 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerSIGN_EXTEND_INREG() local
2763 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType()); in LowerSIGN_EXTEND_INREG()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4666 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerOperation() local
4667 EVT ExtraEltVT = ExtraVT.getVectorElementType(); in LowerOperation()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp47612 EVT ExtraVT = cast<VTSDNode>(N1)->getVT(); in combineSextInRegCmov() local
47614 if (ExtraVT != MVT::i8 && ExtraVT != MVT::i16) in combineSextInRegCmov()
47676 EVT ExtraVT = cast<VTSDNode>(N1)->getVT(); in combineSignExtendInReg() local
47699 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) { in combineSignExtendInReg()