| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 77 ExtractElementInst *Ext1,
79 bool isExtractExtractCheap(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
83 void foldExtExtCmp(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
85 void foldExtExtBinop(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
234 ExtractElementInst *Ext0, ExtractElementInst *Ext1, in getShuffleExtract() argument
237 isa<ConstantInt>(Ext1->getIndexOperand()) && in getShuffleExtract()
241 unsigned Index1 = cast<ConstantInt>(Ext1->getIndexOperand())->getZExtValue(); in getShuffleExtract()
248 assert(VecTy == Ext1->getVectorOperand()->getType() && "Need matching types"); in getShuffleExtract()
252 TTI.getVectorInstrCost(Ext1->getOpcode(), VecTy, Index1); in getShuffleExtract()
264 return Ext1; in getShuffleExtract()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/BinaryFormat/ |
| H A D | MsgPack.def | 94 HANDLE_MP_FIX_LEN(0x01, Ext1)
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/BinaryFormat/ |
| H A D | MsgPackWriter.cpp | 177 case FixLen::Ext1: in writeExt()
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| H A D | MsgPackReader.cpp | 120 return createExt(Obj, FixLen::Ext1); in read()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9689 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
9695 SDValue Res0 = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
9701 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
9703 Res = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
12633 SDValue Ext1 = Mul.getOperand(1); in PerformVQDMULHCombine() local
12635 Ext1.getOpcode() != ISD::SIGN_EXTEND) in PerformVQDMULHCombine()
12640 if (Ext1.getOperand(0).getValueType() != VecVT || in PerformVQDMULHCombine()
12647 Ext1.getOperand(0)); in PerformVQDMULHCombine()
17296 static bool areExtractExts(Value *Ext1, Value *Ext2) { in areExtractExts() argument
17302 if (!match(Ext1, m_ZExtOrSExt(m_Value())) || in areExtractExts()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2568 auto Ext1 = B.buildFPExt(S32, Src1, Flags); in legalizeFPow() local
2571 .addUse(Ext1.getReg(0)) in legalizeFPow()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14009 SDValue Ext1 = FirstInput.getOperand(0); in DAGCombineBuildVector() local
14011 if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in DAGCombineBuildVector()
14015 ConstantSDNode *Ext1Op = dyn_cast<ConstantSDNode>(Ext1.getOperand(1)); in DAGCombineBuildVector()
14019 if (Ext1.getOperand(0).getValueType() != MVT::v4i32 || in DAGCombineBuildVector()
14020 Ext1.getOperand(0) != Ext2.getOperand(0)) in DAGCombineBuildVector()
14033 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 11145 static bool areExtractExts(Value *Ext1, Value *Ext2) { in areExtractExts() argument
11151 if (!match(Ext1, m_ZExtOrSExt(m_Value())) || in areExtractExts()
11153 !areExtDoubled(cast<Instruction>(Ext1)) || in areExtractExts()
11214 auto Ext1 = cast<Instruction>(I->getOperand(0)); in shouldSinkOperands() local
11216 if (areExtractShuffleVectors(Ext1, Ext2)) { in shouldSinkOperands()
11217 Ops.push_back(&Ext1->getOperandUse(0)); in shouldSinkOperands()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 10237 SDValue Ext1 = DAG.getNode(Opcode, DL, VT, Op1); in tryToFoldExtendSelectLoad() local
10239 return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2); in tryToFoldExtendSelectLoad()
18500 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op1, Index); in scalarizeExtractedBinop() local
18501 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 40767 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, in scalarizeExtEltFP() local
40769 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2)); in scalarizeExtEltFP()
40790 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in scalarizeExtEltFP() local
40794 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2); in scalarizeExtEltFP()
50365 SDValue Ext1 = extractSubVector(InVec.getOperand(1), 0, DAG, DL, 128); in combineExtractSubvector() local
50367 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, Ext2); in combineExtractSubvector()
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